From patchwork Fri Jan 5 13:03:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gatien CHEVALLIER X-Patchwork-Id: 13512105 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 72983C3DA6E for ; Fri, 5 Jan 2024 13:05:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ePyrC/B6KgycDYw+JghuLj4fqvJ3UlmVKZSJLl91xS8=; b=1WGnNRZEvPCdbc 5fXfSGwgMjsQBYBx/WuQw+xjR+a4BZNvOuXRQkgt0MFfw/DCoaqOEDmJ9ZFly9aT5ltTzuDOUUuUg Hkg4Ec8XMJAHYhnHK8EfO6I9HD8PjuyijiwRyRa3/qEOqK5PyAwykemfVWIflrry961/m8R8gK9xm iry6mbg7b+5jHKTz+3DWLwdEt6AcZs2IVetSSkqMMzk1/vtgu/oUb3onHVtjAeXbJlZIMkyhS44TG nbRSwG+BBxD4flTCeopk771Kfb3qzJ+OFE4BSM86WCiikzEmz71jBIFrIWz8QrwuAwpJSSuM+6aln w2tpoDsmayb+zCSA2WTw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1rLjsu-00GtlA-2l; Fri, 05 Jan 2024 13:05:12 +0000 Received: from mx07-00178001.pphosted.com ([185.132.182.106]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1rLjso-00GthP-2m; Fri, 05 Jan 2024 13:05:09 +0000 Received: from pps.filterd (m0369458.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 4059PG95028841; Fri, 5 Jan 2024 14:04:37 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=/1plcJCEt4zxfV0bqQNtY/GftB/Ck2iRRS68imm6alM=; b=DM jz1c0ydeFJrkFQ4pJ2SIywze9yA4oTsWh+Khiq16bjyv5h2QGpfz0gGkzg0Nfs1w tQQ1hFfMKiiDD06BteK4zrufwxFmj2pIsuSVPYtIRK50DnQhBMmBpql+CCN0B6yR rOCkgXIoA2uQggC2qnxe8iqohzdKAji+tZyCPRgGbik7kjaag/gLHOlxSDmjeu4N LyryHKnhhFvPimbX6BITfGqLp8LmW6RYzpfsrpr6ouGndcHzdfUFU90ojpLU+KqB ZVtqxrVSHn5OetUlvUveqxspua4XAlJg9pVoEQYpSvh16vHbDSXum8IYU/kL5GbA bKTyRJipvbF/u/dpUBjQ== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3ve9dst5tp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 05 Jan 2024 14:04:37 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 2260810003D; Fri, 5 Jan 2024 14:04:35 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id D8FF6229A90; Fri, 5 Jan 2024 14:04:35 +0100 (CET) Received: from localhost (10.201.20.32) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Fri, 5 Jan 2024 14:04:35 +0100 From: Gatien Chevallier To: , , , , , , , , , , , , , , , , , , , , , , , , , Frank Rowand , , , , , CC: , , , , , , , , , , , , , , , , Gatien Chevallier , Rob Herring Subject: [PATCH v9 03/13] dt-bindings: bus: document RIFSC Date: Fri, 5 Jan 2024 14:03:54 +0100 Message-ID: <20240105130404.301172-4-gatien.chevallier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240105130404.301172-1-gatien.chevallier@foss.st.com> References: <20240105130404.301172-1-gatien.chevallier@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.20.32] X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-05_06,2024-01-05_01,2023-05-22_02 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240105_050507_190592_E002440C X-CRM114-Status: GOOD ( 15.79 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Document RIFSC (RIF security controller). RIFSC is a firewall controller composed of different kinds of hardware resources. Signed-off-by: Gatien Chevallier Reviewed-by: Rob Herring --- Changes in V9: - Added "simple-bus" to RIFSC's compatible list - Added Rob's review tag Changes in V6: - Renamed access-controller to access-controllers - Removal of access-control-provider property - Removal of access-controller and access-controller-names declaration in the patternProperties field. Add additionalProperties: true in this field. Changes in V5: - Renamed feature-domain* to access-control* Changes in V2: - Corrected errors highlighted by Rob's robot - No longer define the maxItems for the "feature-domains" property - Fix example (node name, status) - Declare "feature-domain-names" as an optional property for child nodes - Fix description of "feature-domains" property .../bindings/bus/st,stm32mp25-rifsc.yaml | 105 ++++++++++++++++++ 1 file changed, 105 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml diff --git a/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml b/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml new file mode 100644 index 000000000000..20acd1a6b173 --- /dev/null +++ b/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/st,stm32mp25-rifsc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STM32 Resource isolation framework security controller + +maintainers: + - Gatien Chevallier + +description: | + Resource isolation framework (RIF) is a comprehensive set of hardware blocks + designed to enforce and manage isolation of STM32 hardware resources like + memory and peripherals. + + The RIFSC (RIF security controller) is composed of three sets of registers, + each managing a specific set of hardware resources: + - RISC registers associated with RISUP logic (resource isolation device unit + for peripherals), assign all non-RIF aware peripherals to zero, one or + any security domains (secure, privilege, compartment). + - RIMC registers: associated with RIMU logic (resource isolation master + unit), assign all non RIF-aware bus master to one security domain by + setting secure, privileged and compartment information on the system bus. + Alternatively, the RISUP logic controlling the device port access to a + peripheral can assign target bus attributes to this peripheral master port + (supported attribute: CID). + - RISC registers associated with RISAL logic (resource isolation device unit + for address space - Lite version), assign address space subregions to one + security domains (secure, privilege, compartment). + +select: + properties: + compatible: + contains: + const: st,stm32mp25-rifsc + required: + - compatible + +properties: + compatible: + items: + - const: st,stm32mp25-rifsc + - const: simple-bus + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: true + + "#access-controller-cells": + const: 1 + description: + Contains the firewall ID associated to the peripheral. + +patternProperties: + "^.*@[0-9a-f]+$": + description: Peripherals + type: object + + additionalProperties: true + + required: + - access-controllers + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - "#access-controller-cells" + - ranges + +additionalProperties: false + +examples: + - | + // In this example, the usart2 device refers to rifsc as its domain + // controller. + // Access rights are verified before creating devices. + + #include + + rifsc: bus@42080000 { + compatible = "st,stm32mp25-rifsc", "simple-bus"; + reg = <0x42080000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + #access-controller-cells = <1>; + ranges; + + usart2: serial@400e0000 { + compatible = "st,stm32h7-uart"; + reg = <0x400e0000 0x400>; + interrupts = ; + clocks = <&ck_flexgen_08>; + access-controllers = <&rifsc 32>; + }; + };