| Message ID | 20240108052617.32510-2-praveen.teja.kundanala@amd.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add ZynqMP efuse access support | expand |
On 1/8/24 06:26, Praveen Teja Kundanala wrote: > Add zynqmp_pm_efuse_access API in the ZynqMP > firmware for read/write access of efuse memory. > > Signed-off-by: Praveen Teja Kundanala <praveen.teja.kundanala@amd.com> > --- > drivers/firmware/xilinx/zynqmp.c | 25 +++++++++++++++++++++++++ > include/linux/firmware/xlnx-zynqmp.h | 8 ++++++++ > 2 files changed, 33 insertions(+) > > diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c > index b0d22d4455d9..5abf882a43f5 100644 > --- a/drivers/firmware/xilinx/zynqmp.c > +++ b/drivers/firmware/xilinx/zynqmp.c > @@ -3,6 +3,7 @@ > * Xilinx Zynq MPSoC Firmware layer > * > * Copyright (C) 2014-2022 Xilinx, Inc. > + * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc. > * > * Michal Simek <michal.simek@amd.com> > * Davorin Mista <davorin.mista@aggios.com> > @@ -1435,6 +1436,30 @@ int zynqmp_pm_aes_engine(const u64 address, u32 *out) > } > EXPORT_SYMBOL_GPL(zynqmp_pm_aes_engine); > > +/** > + * zynqmp_pm_efuse_access - Provides access to efuse memory. > + * @address: Address of the efuse params structure > + * @out: Returned output value > + * > + * Return: Returns status, either success or error code. > + */ > +int zynqmp_pm_efuse_access(const u64 address, u32 *out) > +{ > + u32 ret_payload[PAYLOAD_ARG_CNT]; > + int ret; > + > + if (!out) > + return -EINVAL; > + > + ret = zynqmp_pm_invoke_fn(PM_EFUSE_ACCESS, ret_payload, 2, > + upper_32_bits(address), > + lower_32_bits(address)); > + *out = ret_payload[1]; > + > + return ret; > +} > +EXPORT_SYMBOL_GPL(zynqmp_pm_efuse_access); > + > /** > * zynqmp_pm_sha_hash - Access the SHA engine to calculate the hash > * @address: Address of the data/ Address of output buffer where > diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h > index d1ea3898564c..ec3e19065f8d 100644 > --- a/include/linux/firmware/xlnx-zynqmp.h > +++ b/include/linux/firmware/xlnx-zynqmp.h > @@ -3,6 +3,7 @@ > * Xilinx Zynq MPSoC Firmware layer > * > * Copyright (C) 2014-2021 Xilinx > + * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc. > * > * Michal Simek <michal.simek@amd.com> > * Davorin Mista <davorin.mista@aggios.com> > @@ -155,6 +156,7 @@ enum pm_api_id { > PM_CLOCK_GETPARENT = 44, > PM_FPGA_READ = 46, > PM_SECURE_AES = 47, > + PM_EFUSE_ACCESS = 53, > PM_FEATURE_CHECK = 63, > }; > > @@ -546,6 +548,7 @@ int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities, > const u32 qos, > const enum zynqmp_pm_request_ack ack); > int zynqmp_pm_aes_engine(const u64 address, u32 *out); > +int zynqmp_pm_efuse_access(const u64 address, u32 *out); > int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags); > int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags); > int zynqmp_pm_fpga_get_status(u32 *value); > @@ -739,6 +742,11 @@ static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out) > return -ENODEV; > } > > +static inline int zynqmp_pm_efuse_access(const u64 address, u32 *out) > +{ > + return -ENODEV; > +} > + > static inline int zynqmp_pm_sha_hash(const u64 address, const u32 size, > const u32 flags) > { Acked-by: Michal Simek <michal.simek@amd.com> Thanks, Michal
On 1/8/24 06:26, Praveen Teja Kundanala wrote: > Add zynqmp_pm_efuse_access API in the ZynqMP > firmware for read/write access of efuse memory. > > Signed-off-by: Praveen Teja Kundanala <praveen.teja.kundanala@amd.com> > --- > drivers/firmware/xilinx/zynqmp.c | 25 +++++++++++++++++++++++++ > include/linux/firmware/xlnx-zynqmp.h | 8 ++++++++ > 2 files changed, 33 insertions(+) > > diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c > index b0d22d4455d9..5abf882a43f5 100644 > --- a/drivers/firmware/xilinx/zynqmp.c > +++ b/drivers/firmware/xilinx/zynqmp.c > @@ -3,6 +3,7 @@ > * Xilinx Zynq MPSoC Firmware layer > * > * Copyright (C) 2014-2022 Xilinx, Inc. > + * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc. > * > * Michal Simek <michal.simek@amd.com> > * Davorin Mista <davorin.mista@aggios.com> > @@ -1435,6 +1436,30 @@ int zynqmp_pm_aes_engine(const u64 address, u32 *out) > } > EXPORT_SYMBOL_GPL(zynqmp_pm_aes_engine); > > +/** > + * zynqmp_pm_efuse_access - Provides access to efuse memory. > + * @address: Address of the efuse params structure > + * @out: Returned output value > + * > + * Return: Returns status, either success or error code. > + */ > +int zynqmp_pm_efuse_access(const u64 address, u32 *out) > +{ > + u32 ret_payload[PAYLOAD_ARG_CNT]; > + int ret; > + > + if (!out) > + return -EINVAL; > + > + ret = zynqmp_pm_invoke_fn(PM_EFUSE_ACCESS, ret_payload, 2, > + upper_32_bits(address), > + lower_32_bits(address)); > + *out = ret_payload[1]; > + > + return ret; > +} > +EXPORT_SYMBOL_GPL(zynqmp_pm_efuse_access); > + > /** > * zynqmp_pm_sha_hash - Access the SHA engine to calculate the hash > * @address: Address of the data/ Address of output buffer where > diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h > index d1ea3898564c..ec3e19065f8d 100644 > --- a/include/linux/firmware/xlnx-zynqmp.h > +++ b/include/linux/firmware/xlnx-zynqmp.h > @@ -3,6 +3,7 @@ > * Xilinx Zynq MPSoC Firmware layer > * > * Copyright (C) 2014-2021 Xilinx > + * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc. > * > * Michal Simek <michal.simek@amd.com> > * Davorin Mista <davorin.mista@aggios.com> > @@ -155,6 +156,7 @@ enum pm_api_id { > PM_CLOCK_GETPARENT = 44, > PM_FPGA_READ = 46, > PM_SECURE_AES = 47, > + PM_EFUSE_ACCESS = 53, > PM_FEATURE_CHECK = 63, > }; > > @@ -546,6 +548,7 @@ int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities, > const u32 qos, > const enum zynqmp_pm_request_ack ack); > int zynqmp_pm_aes_engine(const u64 address, u32 *out); > +int zynqmp_pm_efuse_access(const u64 address, u32 *out); > int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags); > int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags); > int zynqmp_pm_fpga_get_status(u32 *value); > @@ -739,6 +742,11 @@ static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out) > return -ENODEV; > } > > +static inline int zynqmp_pm_efuse_access(const u64 address, u32 *out) > +{ > + return -ENODEV; > +} > + > static inline int zynqmp_pm_sha_hash(const u64 address, const u32 size, > const u32 flags) > { Acked-by: Michal Simek <michal.simek@amd.com> Thanks, Michal
diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c index b0d22d4455d9..5abf882a43f5 100644 --- a/drivers/firmware/xilinx/zynqmp.c +++ b/drivers/firmware/xilinx/zynqmp.c @@ -3,6 +3,7 @@ * Xilinx Zynq MPSoC Firmware layer * * Copyright (C) 2014-2022 Xilinx, Inc. + * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> * Davorin Mista <davorin.mista@aggios.com> @@ -1435,6 +1436,30 @@ int zynqmp_pm_aes_engine(const u64 address, u32 *out) } EXPORT_SYMBOL_GPL(zynqmp_pm_aes_engine); +/** + * zynqmp_pm_efuse_access - Provides access to efuse memory. + * @address: Address of the efuse params structure + * @out: Returned output value + * + * Return: Returns status, either success or error code. + */ +int zynqmp_pm_efuse_access(const u64 address, u32 *out) +{ + u32 ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + if (!out) + return -EINVAL; + + ret = zynqmp_pm_invoke_fn(PM_EFUSE_ACCESS, ret_payload, 2, + upper_32_bits(address), + lower_32_bits(address)); + *out = ret_payload[1]; + + return ret; +} +EXPORT_SYMBOL_GPL(zynqmp_pm_efuse_access); + /** * zynqmp_pm_sha_hash - Access the SHA engine to calculate the hash * @address: Address of the data/ Address of output buffer where diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index d1ea3898564c..ec3e19065f8d 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -3,6 +3,7 @@ * Xilinx Zynq MPSoC Firmware layer * * Copyright (C) 2014-2021 Xilinx + * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> * Davorin Mista <davorin.mista@aggios.com> @@ -155,6 +156,7 @@ enum pm_api_id { PM_CLOCK_GETPARENT = 44, PM_FPGA_READ = 46, PM_SECURE_AES = 47, + PM_EFUSE_ACCESS = 53, PM_FEATURE_CHECK = 63, }; @@ -546,6 +548,7 @@ int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities, const u32 qos, const enum zynqmp_pm_request_ack ack); int zynqmp_pm_aes_engine(const u64 address, u32 *out); +int zynqmp_pm_efuse_access(const u64 address, u32 *out); int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags); int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags); int zynqmp_pm_fpga_get_status(u32 *value); @@ -739,6 +742,11 @@ static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out) return -ENODEV; } +static inline int zynqmp_pm_efuse_access(const u64 address, u32 *out) +{ + return -ENODEV; +} + static inline int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags) {
Add zynqmp_pm_efuse_access API in the ZynqMP firmware for read/write access of efuse memory. Signed-off-by: Praveen Teja Kundanala <praveen.teja.kundanala@amd.com> --- drivers/firmware/xilinx/zynqmp.c | 25 +++++++++++++++++++++++++ include/linux/firmware/xlnx-zynqmp.h | 8 ++++++++ 2 files changed, 33 insertions(+)