| Message ID | 20240123161718.3921974-1-ryan.roberts@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v1] arm64/mm: Make set_ptes() robust when OAs cross 48-bit boundary | expand |
On 23.01.24 17:17, Ryan Roberts wrote: > Since the high bits [51:48] of an OA are not stored contiguously in the > PTE, there is a theoretical bug in set_ptes(), which just adds PAGE_SIZE > to the pte to get the pte with the next pfn. This works until the pfn > crosses the 48-bit boundary, at which point we overflow into the upper > attributes. > > Of course one could argue (and Matthew Wilcox has :) that we will never > see a folio cross this boundary because we only allow naturally aligned > power-of-2 allocation, so this would require a half-petabyte folio. So > its only a theoretical bug. But its better that the code is robust > regardless. > > I've implemented pte_next_pfn() as part of the fix, which is an opt-in > core-mm interface. So that is now available to the core-mm, which will > be needed shortly to support forthcoming fork()-batching optimizations. > > pte_pgprot() wasn't particularly optimal when compiling for 52-bit PAs, > so I've reimplemented that using PTE_ADDR_MASK. This saves 2 > instructions in pte_next_pfn(); 12 down to 10. When compiling for 48-bit > addresses, the generated code is the same (5 instructions). > > Fixes: 4a169d61c2ed ("arm64: implement the new page table range API") > Closes: https://lore.kernel.org/linux-mm/fdaeb9a5-d890-499a-92c8-d171df43ad01@arm.com/ > Signed-off-by: Ryan Roberts <ryan.roberts@arm.com> > --- > > Hi All, > > This applies on top of v6.8-rc1. It's a dependency for David's fork-batch > work, so it would be preferable to go through the mm tree, once it has been > acked by Catalin or Will. > > Thanks, > Ryan > Reviewed-by: David Hildenbrand <david@redhat.com>
On Tue, Jan 23, 2024 at 04:17:18PM +0000, Ryan Roberts wrote: > diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h > index 79ce70fbb751..734b39401a05 100644 > --- a/arch/arm64/include/asm/pgtable.h > +++ b/arch/arm64/include/asm/pgtable.h > @@ -92,6 +92,14 @@ static inline pteval_t __phys_to_pte_val(phys_addr_t phys) > #define pfn_pte(pfn,prot) \ > __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) > > +/* > + * Select all bits except the pfn > + */ > +static inline pgprot_t pte_pgprot(pte_t pte) > +{ > + return __pgprot(pte_val(pte) & ~PTE_ADDR_MASK); > +} > + > #define pte_none(pte) (!pte_val(pte)) > #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0)) > #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) > @@ -341,6 +349,12 @@ static inline void __sync_cache_and_tags(pte_t pte, unsigned int nr_pages) > mte_sync_tags(pte, nr_pages); > } > > +#define pte_next_pfn pte_next_pfn > +static inline pte_t pte_next_pfn(pte_t pte) > +{ > + return pfn_pte(pte_pfn(pte) + 1, pte_pgprot(pte)); > +} While I see why you wanted to optimise this, I'd rather keep the pte_pgprot() change separate and at a later time. This will conflict (fail to build) with Ard's patch removing PTE_ADDR_MASK: https://lore.kernel.org/all/20240123145258.1462979-89-ardb+git@google.com/ This masking out is no longer straightforward with support for LPA2 (especially the 52-bit physical addresses with 4K pages): bits 8 and 9 of the PTE either contain bits 50, 51 of the PA or the shareability attribute if FEAT_LPA2 is not present. In the latter case, we need them preserved.
On 25/01/2024 17:07, Catalin Marinas wrote: > On Tue, Jan 23, 2024 at 04:17:18PM +0000, Ryan Roberts wrote: >> diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h >> index 79ce70fbb751..734b39401a05 100644 >> --- a/arch/arm64/include/asm/pgtable.h >> +++ b/arch/arm64/include/asm/pgtable.h >> @@ -92,6 +92,14 @@ static inline pteval_t __phys_to_pte_val(phys_addr_t phys) >> #define pfn_pte(pfn,prot) \ >> __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) >> >> +/* >> + * Select all bits except the pfn >> + */ >> +static inline pgprot_t pte_pgprot(pte_t pte) >> +{ >> + return __pgprot(pte_val(pte) & ~PTE_ADDR_MASK); >> +} >> + >> #define pte_none(pte) (!pte_val(pte)) >> #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0)) >> #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) >> @@ -341,6 +349,12 @@ static inline void __sync_cache_and_tags(pte_t pte, unsigned int nr_pages) >> mte_sync_tags(pte, nr_pages); >> } >> >> +#define pte_next_pfn pte_next_pfn >> +static inline pte_t pte_next_pfn(pte_t pte) >> +{ >> + return pfn_pte(pte_pfn(pte) + 1, pte_pgprot(pte)); >> +} > > While I see why you wanted to optimise this, I'd rather keep the > pte_pgprot() change separate and at a later time. This will conflict > (fail to build) with Ard's patch removing PTE_ADDR_MASK: OK fair enough. I'll respin it without the pte_pgprot() change. Thanks for the review. > > https://lore.kernel.org/all/20240123145258.1462979-89-ardb+git@google.com/ > > This masking out is no longer straightforward with support for LPA2 > (especially the 52-bit physical addresses with 4K pages): bits 8 and 9 > of the PTE either contain bits 50, 51 of the PA or the shareability > attribute if FEAT_LPA2 is not present. In the latter case, we need them > preserved. >
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h index 79ce70fbb751..734b39401a05 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -92,6 +92,14 @@ static inline pteval_t __phys_to_pte_val(phys_addr_t phys) #define pfn_pte(pfn,prot) \ __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) +/* + * Select all bits except the pfn + */ +static inline pgprot_t pte_pgprot(pte_t pte) +{ + return __pgprot(pte_val(pte) & ~PTE_ADDR_MASK); +} + #define pte_none(pte) (!pte_val(pte)) #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0)) #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) @@ -341,6 +349,12 @@ static inline void __sync_cache_and_tags(pte_t pte, unsigned int nr_pages) mte_sync_tags(pte, nr_pages); } +#define pte_next_pfn pte_next_pfn +static inline pte_t pte_next_pfn(pte_t pte) +{ + return pfn_pte(pte_pfn(pte) + 1, pte_pgprot(pte)); +} + static inline void set_ptes(struct mm_struct *mm, unsigned long __always_unused addr, pte_t *ptep, pte_t pte, unsigned int nr) @@ -354,7 +368,7 @@ static inline void set_ptes(struct mm_struct *mm, if (--nr == 0) break; ptep++; - pte_val(pte) += PAGE_SIZE; + pte = pte_next_pfn(pte); } } #define set_ptes set_ptes @@ -433,16 +447,6 @@ static inline pte_t pte_swp_clear_exclusive(pte_t pte) return clear_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); } -/* - * Select all bits except the pfn - */ -static inline pgprot_t pte_pgprot(pte_t pte) -{ - unsigned long pfn = pte_pfn(pte); - - return __pgprot(pte_val(pfn_pte(pfn, __pgprot(0))) ^ pte_val(pte)); -} - #ifdef CONFIG_NUMA_BALANCING /* * See the comment in include/linux/pgtable.h
Since the high bits [51:48] of an OA are not stored contiguously in the PTE, there is a theoretical bug in set_ptes(), which just adds PAGE_SIZE to the pte to get the pte with the next pfn. This works until the pfn crosses the 48-bit boundary, at which point we overflow into the upper attributes. Of course one could argue (and Matthew Wilcox has :) that we will never see a folio cross this boundary because we only allow naturally aligned power-of-2 allocation, so this would require a half-petabyte folio. So its only a theoretical bug. But its better that the code is robust regardless. I've implemented pte_next_pfn() as part of the fix, which is an opt-in core-mm interface. So that is now available to the core-mm, which will be needed shortly to support forthcoming fork()-batching optimizations. pte_pgprot() wasn't particularly optimal when compiling for 52-bit PAs, so I've reimplemented that using PTE_ADDR_MASK. This saves 2 instructions in pte_next_pfn(); 12 down to 10. When compiling for 48-bit addresses, the generated code is the same (5 instructions). Fixes: 4a169d61c2ed ("arm64: implement the new page table range API") Closes: https://lore.kernel.org/linux-mm/fdaeb9a5-d890-499a-92c8-d171df43ad01@arm.com/ Signed-off-by: Ryan Roberts <ryan.roberts@arm.com> --- Hi All, This applies on top of v6.8-rc1. It's a dependency for David's fork-batch work, so it would be preferable to go through the mm tree, once it has been acked by Catalin or Will. Thanks, Ryan arch/arm64/include/asm/pgtable.h | 26 +++++++++++++++----------- 1 file changed, 15 insertions(+), 11 deletions(-) -- 2.25.1