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Thu, 25 Jan 2024 21:05:13 GMT Received: from [169.254.0.1] (10.49.16.6) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 25 Jan 2024 13:05:13 -0800 From: Bjorn Andersson Date: Thu, 25 Jan 2024 13:05:12 -0800 Subject: [PATCH v4 6/8] arm64: dts: qcom: sa8295p-adp: add max20411 MIME-Version: 1.0 Message-ID: <20240125-sa8295p-gpu-v4-6-7011c2a63037@quicinc.com> References: <20240125-sa8295p-gpu-v4-0-7011c2a63037@quicinc.com> In-Reply-To: <20240125-sa8295p-gpu-v4-0-7011c2a63037@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Taniya Das , Johan Hovold CC: , , , , , , "Bjorn Andersson" , Bjorn Andersson X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1706216711; l=1705; i=quic_bjorande@quicinc.com; s=20230915; h=from:subject:message-id; bh=9G8OC71Bo5Qk4jp3jd+PoCQTayjd12YeJaxENqcceCg=; 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Enable the bus and add the maxim,max20411 device on the bus. Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 39 ++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts index fd253942e5e5..bd0962f39fc5 100644 --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts @@ -266,6 +266,26 @@ &dispcc1 { status = "okay"; }; +&i2c12 { + pinctrl-0 = <&qup1_i2c4_state>; + pinctrl-names = "default"; + + status = "okay"; + + vdd_gfx: regulator@39 { + compatible = "maxim,max20411"; + reg = <0x39>; + + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + + enable-gpios = <&pmm8540a_gpios 2 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&max20411_en>; + pinctrl-names = "default"; + }; +}; + &mdss0 { status = "okay"; }; @@ -476,6 +496,10 @@ &pcie4_phy { status = "okay"; }; +&qup1 { + status = "okay"; +}; + &qup2 { status = "okay"; }; @@ -636,6 +660,14 @@ &xo_board_clk { /* PINCTRL */ +&pmm8540a_gpios { + max20411_en: max20411-en-state { + pins = "gpio2"; + function = "normal"; + output-enable; + }; +}; + &tlmm { pcie2a_default: pcie2a-default-state { clkreq-n-pins { @@ -728,4 +760,11 @@ wake-n-pins { bias-pull-up; }; }; + + qup1_i2c4_state: qup1-i2c4-state { + pins = "gpio0", "gpio1"; + function = "qup12"; + drive-strength = <2>; + bias-pull-up; + }; };