diff mbox series

[3/3] arm64: dts: ti: Add DT overlay for PCIe + USB3.0 SERDES personality card

Message ID 20240126114530.40913-4-rogerq@kernel.org (mailing list archive)
State New, archived
Headers show
Series arm64: dts: ti: am65x: Add PCIe + USB DT overlay files | expand

Commit Message

Roger Quadros Jan. 26, 2024, 11:45 a.m. UTC 
From: Kishon Vijay Abraham I <kishon@ti.com>

Add overlay for PCIe (uses the second instance of PCIe in AM654x) and
USB3.0 SERDES personality card

The PCI3/USB3 card is provided with the AM65x GP EVM configurtion [1]
so apply the overlay to k3-am654-gp-evm.dtb

[1] https://www.ti.com/lit/ug/spruim7/spruim7.pdf

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Roger Quadros <rogerq@kernel.org>
---
 arch/arm64/boot/dts/ti/Makefile               |  5 +-
 .../arm64/boot/dts/ti/k3-am654-pcie-usb3.dtso | 67 +++++++++++++++++++
 2 files changed, 71 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm64/boot/dts/ti/k3-am654-pcie-usb3.dtso

Comments

Vignesh Raghavendra Feb. 5, 2024, 2:46 p.m. UTC | #1 
On 26/01/24 17:15, Roger Quadros wrote:
> From: Kishon Vijay Abraham I <kishon@ti.com>
> 

[...]

>  # Boards with J7200 SoC
>  k3-j7200-evm-dtbs := k3-j7200-common-proc-board.dtb k3-j7200-evm-quad-port-eth-exp.dtbo
> diff --git a/arch/arm64/boot/dts/ti/k3-am654-pcie-usb3.dtso b/arch/arm64/boot/dts/ti/k3-am654-pcie-usb3.dtso
> new file mode 100644
> index 000000000000..c63b7241c005
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-am654-pcie-usb3.dtso
> @@ -0,0 +1,67 @@
> +// SPDX-License-Identifier: GPL-2.0-only OR MIT
> +/**
> + * DT overlay for SERDES personality card: 1lane PCIe + USB3.0 DRD on AM654 EVM
> + *
> + * Copyright (C) 2018-2024 Texas Instruments Incorporated - http://www.ti.com/
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/phy/phy.h>
> +#include <dt-bindings/phy/phy-am654-serdes.h>
> +
> +#include "k3-pinctrl.h"
> +
> +&serdes1 {
> +	status = "okay";
> +};
> +
> +&pcie1_rc {
> +	num-lanes = <1>;
> +	phys = <&serdes1 PHY_TYPE_PCIE 0>;
> +	phy-names = "pcie-phy0";
> +	reset-gpios = <&pca9555 5 GPIO_ACTIVE_HIGH>;
> +	status = "okay";
> +};
> +
> +&pcie1_ep {
> +	num-lanes = <1>;
> +	phys = <&serdes1 PHY_TYPE_PCIE 0>;
> +	phy-names = "pcie-phy0";
> +};
> +
> +&main_pmx0 {
> +	usb0_pins_default: usb0_pins_default {

No underscores in node-name and also should end with -pins

> +		pinctrl-single,pins = <
> +			AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
> +		>;
> +	};
> +};
> +
> +&serdes0 {
> +	status = "okay";
> +	assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
> +	assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>;
> +};
> +
> +&dwc3_0 {
> +	status = "okay";
> +	assigned-clock-parents = <&k3_clks 151 4>,      /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
> +	<&k3_clks 151 8>;      /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */
> +	phys = <&serdes0 PHY_TYPE_USB3 0>;
> +	phy-names = "usb3-phy";
> +};
> +
> +&usb0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&usb0_pins_default>;
> +	dr_mode = "host";
> +	maximum-speed = "super-speed";
> +	snps,dis-u1-entry-quirk;
> +	snps,dis-u2-entry-quirk;
> +};
> +
> +&usb0_phy {
> +	status = "okay";
> +};


BTW, this breaks build on 6.8-rc1


  DTOVL   arch/arm64/boot/dts/ti/k3-am654-gp-evm.dtb

Failed to apply 'arch/arm64/boot/dts/ti/k3-am654-pcie-usb3.dtbo': FDT_ERR_NOTFOUND
Roger Quadros Feb. 6, 2024, 1:36 p.m. UTC | #2 
On 05/02/2024 16:46, Vignesh Raghavendra wrote:
> 
> 
> On 26/01/24 17:15, Roger Quadros wrote:
>> From: Kishon Vijay Abraham I <kishon@ti.com>
>>
> 
> [...]
> 
>>  # Boards with J7200 SoC
>>  k3-j7200-evm-dtbs := k3-j7200-common-proc-board.dtb k3-j7200-evm-quad-port-eth-exp.dtbo
>> diff --git a/arch/arm64/boot/dts/ti/k3-am654-pcie-usb3.dtso b/arch/arm64/boot/dts/ti/k3-am654-pcie-usb3.dtso
>> new file mode 100644
>> index 000000000000..c63b7241c005
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/ti/k3-am654-pcie-usb3.dtso
>> @@ -0,0 +1,67 @@
>> +// SPDX-License-Identifier: GPL-2.0-only OR MIT
>> +/**
>> + * DT overlay for SERDES personality card: 1lane PCIe + USB3.0 DRD on AM654 EVM
>> + *
>> + * Copyright (C) 2018-2024 Texas Instruments Incorporated - http://www.ti.com/
>> + */
>> +
>> +/dts-v1/;
>> +/plugin/;
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/phy/phy.h>
>> +#include <dt-bindings/phy/phy-am654-serdes.h>
>> +
>> +#include "k3-pinctrl.h"
>> +
>> +&serdes1 {
>> +	status = "okay";
>> +};
>> +
>> +&pcie1_rc {
>> +	num-lanes = <1>;
>> +	phys = <&serdes1 PHY_TYPE_PCIE 0>;
>> +	phy-names = "pcie-phy0";
>> +	reset-gpios = <&pca9555 5 GPIO_ACTIVE_HIGH>;
>> +	status = "okay";
>> +};
>> +
>> +&pcie1_ep {
>> +	num-lanes = <1>;
>> +	phys = <&serdes1 PHY_TYPE_PCIE 0>;
>> +	phy-names = "pcie-phy0";
>> +};
>> +
>> +&main_pmx0 {
>> +	usb0_pins_default: usb0_pins_default {
> 
> No underscores in node-name and also should end with -pins
> 
>> +		pinctrl-single,pins = <
>> +			AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
>> +		>;
>> +	};
>> +};
>> +
>> +&serdes0 {
>> +	status = "okay";
>> +	assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
>> +	assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>;
>> +};
>> +
>> +&dwc3_0 {
>> +	status = "okay";
>> +	assigned-clock-parents = <&k3_clks 151 4>,      /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
>> +	<&k3_clks 151 8>;      /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */
>> +	phys = <&serdes0 PHY_TYPE_USB3 0>;
>> +	phy-names = "usb3-phy";
>> +};
>> +
>> +&usb0 {
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&usb0_pins_default>;
>> +	dr_mode = "host";
>> +	maximum-speed = "super-speed";
>> +	snps,dis-u1-entry-quirk;
>> +	snps,dis-u2-entry-quirk;
>> +};
>> +
>> +&usb0_phy {
>> +	status = "okay";
>> +};
> 
> 
> BTW, this breaks build on 6.8-rc1
> 
> 
>   DTOVL   arch/arm64/boot/dts/ti/k3-am654-gp-evm.dtb
> 
> Failed to apply 'arch/arm64/boot/dts/ti/k3-am654-pcie-usb3.dtbo': FDT_ERR_NOTFOUND
> 
> 

It builds fine for me. Did the 3rd patch apply cleanly for you?
Vignesh Raghavendra Feb. 8, 2024, 4:24 a.m. UTC | #3 
On 06/02/24 19:06, Roger Quadros wrote:
> 
> 
> On 05/02/2024 16:46, Vignesh Raghavendra wrote:
>>
>>
>> On 26/01/24 17:15, Roger Quadros wrote:
>>> From: Kishon Vijay Abraham I <kishon@ti.com>
>>>
>>
>> [...]
>>
>>>  # Boards with J7200 SoC
>>>  k3-j7200-evm-dtbs := k3-j7200-common-proc-board.dtb k3-j7200-evm-quad-port-eth-exp.dtbo
>>> diff --git a/arch/arm64/boot/dts/ti/k3-am654-pcie-usb3.dtso b/arch/arm64/boot/dts/ti/k3-am654-pcie-usb3.dtso
>>> new file mode 100644
>>> index 000000000000..c63b7241c005
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/ti/k3-am654-pcie-usb3.dtso
>>> @@ -0,0 +1,67 @@
>>> +// SPDX-License-Identifier: GPL-2.0-only OR MIT
>>> +/**
>>> + * DT overlay for SERDES personality card: 1lane PCIe + USB3.0 DRD on AM654 EVM
>>> + *
>>> + * Copyright (C) 2018-2024 Texas Instruments Incorporated - http://www.ti.com/
>>> + */
>>> +
>>> +/dts-v1/;
>>> +/plugin/;
>>> +#include <dt-bindings/gpio/gpio.h>
>>> +#include <dt-bindings/phy/phy.h>
>>> +#include <dt-bindings/phy/phy-am654-serdes.h>
>>> +
>>> +#include "k3-pinctrl.h"
>>> +
>>> +&serdes1 {
>>> +	status = "okay";
>>> +};
>>> +
>>> +&pcie1_rc {
>>> +	num-lanes = <1>;
>>> +	phys = <&serdes1 PHY_TYPE_PCIE 0>;
>>> +	phy-names = "pcie-phy0";
>>> +	reset-gpios = <&pca9555 5 GPIO_ACTIVE_HIGH>;
>>> +	status = "okay";
>>> +};
>>> +
>>> +&pcie1_ep {
>>> +	num-lanes = <1>;
>>> +	phys = <&serdes1 PHY_TYPE_PCIE 0>;
>>> +	phy-names = "pcie-phy0";
>>> +};
>>> +
>>> +&main_pmx0 {
>>> +	usb0_pins_default: usb0_pins_default {
>>
>> No underscores in node-name and also should end with -pins
>>
>>> +		pinctrl-single,pins = <
>>> +			AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
>>> +		>;
>>> +	};
>>> +};
>>> +
>>> +&serdes0 {
>>> +	status = "okay";
>>> +	assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
>>> +	assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>;
>>> +};
>>> +
>>> +&dwc3_0 {
>>> +	status = "okay";
>>> +	assigned-clock-parents = <&k3_clks 151 4>,      /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
>>> +	<&k3_clks 151 8>;      /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */
>>> +	phys = <&serdes0 PHY_TYPE_USB3 0>;
>>> +	phy-names = "usb3-phy";
>>> +};
>>> +
>>> +&usb0 {
>>> +	pinctrl-names = "default";
>>> +	pinctrl-0 = <&usb0_pins_default>;
>>> +	dr_mode = "host";
>>> +	maximum-speed = "super-speed";
>>> +	snps,dis-u1-entry-quirk;
>>> +	snps,dis-u2-entry-quirk;
>>> +};
>>> +
>>> +&usb0_phy {
>>> +	status = "okay";
>>> +};
>>
>>
>> BTW, this breaks build on 6.8-rc1
>>
>>
>>   DTOVL   arch/arm64/boot/dts/ti/k3-am654-gp-evm.dtb
>>
>> Failed to apply 'arch/arm64/boot/dts/ti/k3-am654-pcie-usb3.dtbo': FDT_ERR_NOTFOUND
>>
>>
> 
> It builds fine for me. Did the 3rd patch apply cleanly for you?
> 


Yes, build failure is due to the fact that I picked up Andrew's patch to
remove pcie_ep node. Could you please respin this on top of ti-next /
linux-next?

--
Regards
Vignesh
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 3c008623b693..91fc14044ee3 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -45,7 +45,9 @@  dtb-$(CONFIG_ARCH_K3) += k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo
 dtb-$(CONFIG_ARCH_K3) += k3-am64-tqma64xxl-mbax4xxl-wlan.dtbo
 
 # Boards with AM65x SoC
-k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb k3-am654-base-board-rocktech-rk101-panel.dtbo
+k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb \
+	k3-am654-base-board-rocktech-rk101-panel.dtbo \
+	k3-am654-pcie-usb3.dtbo
 k3-am654-evm-dtbs := k3-am654-base-board.dtb k3-am654-icssg2.dtbo
 k3-am654-idk-dtbs := k3-am654-evm.dtb k3-am654-idk.dtbo k3-am654-pcie-usb2.dtbo
 dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic.dtb
@@ -59,6 +61,7 @@  dtb-$(CONFIG_ARCH_K3) += k3-am654-evm.dtb
 dtb-$(CONFIG_ARCH_K3) += k3-am654-idk.dtb
 dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board-rocktech-rk101-panel.dtbo
 dtb-$(CONFIG_ARCH_K3) += k3-am654-pcie-usb2.dtbo
+dtb-$(CONFIG_ARCH_K3) += k3-am654-pcie-usb3.dtbo
 
 # Boards with J7200 SoC
 k3-j7200-evm-dtbs := k3-j7200-common-proc-board.dtb k3-j7200-evm-quad-port-eth-exp.dtbo
diff --git a/arch/arm64/boot/dts/ti/k3-am654-pcie-usb3.dtso b/arch/arm64/boot/dts/ti/k3-am654-pcie-usb3.dtso
new file mode 100644
index 000000000000..c63b7241c005
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am654-pcie-usb3.dtso
@@ -0,0 +1,67 @@ 
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/**
+ * DT overlay for SERDES personality card: 1lane PCIe + USB3.0 DRD on AM654 EVM
+ *
+ * Copyright (C) 2018-2024 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/phy/phy-am654-serdes.h>
+
+#include "k3-pinctrl.h"
+
+&serdes1 {
+	status = "okay";
+};
+
+&pcie1_rc {
+	num-lanes = <1>;
+	phys = <&serdes1 PHY_TYPE_PCIE 0>;
+	phy-names = "pcie-phy0";
+	reset-gpios = <&pca9555 5 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&pcie1_ep {
+	num-lanes = <1>;
+	phys = <&serdes1 PHY_TYPE_PCIE 0>;
+	phy-names = "pcie-phy0";
+};
+
+&main_pmx0 {
+	usb0_pins_default: usb0_pins_default {
+		pinctrl-single,pins = <
+			AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
+		>;
+	};
+};
+
+&serdes0 {
+	status = "okay";
+	assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
+	assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>;
+};
+
+&dwc3_0 {
+	status = "okay";
+	assigned-clock-parents = <&k3_clks 151 4>,      /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
+	<&k3_clks 151 8>;      /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */
+	phys = <&serdes0 PHY_TYPE_USB3 0>;
+	phy-names = "usb3-phy";
+};
+
+&usb0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb0_pins_default>;
+	dr_mode = "host";
+	maximum-speed = "super-speed";
+	snps,dis-u1-entry-quirk;
+	snps,dis-u2-entry-quirk;
+};
+
+&usb0_phy {
+	status = "okay";
+};