| Message ID | 20240130093812.1746512-6-andre.draszik@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | gs101 oriole: peripheral block 0 (peric0) fixes | expand |
On 30/01/2024 10:36, André Draszik wrote: > The peric0_top1_ipclk_0 and peric0_top1_pclk_0 are the clocks going to > peric0/uart_usi, with pclk being the bus clock. Without pclk running, > any bus access will hang. > Unfortunately, in commit d97b6c902a40 ("arm64: dts: exynos: gs101: > update USI UART to use peric0 clocks") the gs101 DT ended up specifying > an incorrect pclk in the respective node and instead the two clocks > here were marked as critical. > > We have fixed the gs101 DT and can therefore drop this incorrect > work-around here, the uart driver will claim these clocks as needed. How did you fixed the DTS? Which commit did it? Are we going back to basics of driver changes depending on DTS? Best regards, Krzysztof
Hi Krzysztof, On Thu, 2024-02-01 at 11:02 +0100, Krzysztof Kozlowski wrote: > On 30/01/2024 10:36, André Draszik wrote: > > The peric0_top1_ipclk_0 and peric0_top1_pclk_0 are the clocks going to > > peric0/uart_usi, with pclk being the bus clock. Without pclk running, > > any bus access will hang. > > Unfortunately, in commit d97b6c902a40 ("arm64: dts: exynos: gs101: > > update USI UART to use peric0 clocks") the gs101 DT ended up specifying > > an incorrect pclk in the respective node and instead the two clocks > > here were marked as critical. > > > > We have fixed the gs101 DT and can therefore drop this incorrect > > work-around here, the uart driver will claim these clocks as needed. > > How did you fixed the DTS? Which commit did it? Are we going back to > basics of driver changes depending on DTS? Sorry if the description isn't clear. a) these clocks are not critical for the system to work, and this patch fixes that. b) the initial DTSI for gs101 used incorrect clocks for the serial, and it didn't work. The work-around was to specify these clocks here as critical instead. Patch #4 in this series has corrected the DTSI. So there is no dependency between the DTS update and the driver update here as such, no new properties, or otherwise. That said, now that b) above has been fixed (in patch #4), it is OK to mark these clocks as non-critical without any ill effects. That's all that is happening. I was merely referencing that in the commit message. I can rephrase things if you wish. Cheers, Andre'
diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c index 61bb0dcf84ee..5c338ac9231c 100644 --- a/drivers/clk/samsung/clk-gs101.c +++ b/drivers/clk/samsung/clk-gs101.c @@ -2982,20 +2982,18 @@ static const struct samsung_gate_clock peric0_gate_clks[] __initconst = { "gout_peric0_peric0_top0_pclk_9", "mout_peric0_bus_user", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9, 21, 0, 0), - /* Disabling this clock makes the system hang. Mark the clock as critical. */ GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0, "gout_peric0_peric0_top1_ipclk_0", "dout_peric0_usi0_uart", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0, - 21, CLK_IS_CRITICAL, 0), + 21, 0, 0), GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2, "gout_peric0_peric0_top1_ipclk_2", "dout_peric0_usi14_usi", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2, 21, 0, 0), - /* Disabling this clock makes the system hang. Mark the clock as critical. */ GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0, "gout_peric0_peric0_top1_pclk_0", "mout_peric0_bus_user", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0, - 21, CLK_IS_CRITICAL, 0), + 21, 0, 0), GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2, "gout_peric0_peric0_top1_pclk_2", "mout_peric0_bus_user", CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2,
The peric0_top1_ipclk_0 and peric0_top1_pclk_0 are the clocks going to peric0/uart_usi, with pclk being the bus clock. Without pclk running, any bus access will hang. Unfortunately, in commit d97b6c902a40 ("arm64: dts: exynos: gs101: update USI UART to use peric0 clocks") the gs101 DT ended up specifying an incorrect pclk in the respective node and instead the two clocks here were marked as critical. We have fixed the gs101 DT and can therefore drop this incorrect work-around here, the uart driver will claim these clocks as needed. Note that this commit has the side-effect of causing earlycon to stop to work sometime into the boot for two reasons: * peric0_top1_ipclk_0 requires its parent gout_cmu_peric0_ip to be running, but because earlycon doesn't deal with clocks that parent will be disabled when none of the other drivers that actually deal with clocks correctly require it to be running and the real serial driver (which does deal with clocks) hasn't taken over yet * hand-over between earlycon and serial driver appears to be fragile and clocks get enabled and disabled a few times, which also causes register access to hang while earlycon is still active Nonetheless we shouldn't keep these clocks running unconditionally just for earlycon. Clocks should be disabled where possible. If earlycon is required in the future, e.g. for debug, this commit can simply be reverted (locally!). Fixes: 893f133a040b ("clk: samsung: gs101: add support for cmu_peric0") Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> --- v2: * collect Reviewed-by: tags --- drivers/clk/samsung/clk-gs101.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-)