@@ -45,6 +45,19 @@ clk_xtal25: clock-xtal25 {
clock-frequency = <25000000>;
};
+ clk_pwm4: clock-pwm4 {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12000000>;
+ clock-output-names = "codec-pwm4";
+ /*
+ * 1 / 83 ns ~= 12 MHz , but since the PWM input clock is 24 MHz
+ * and the calculated PWM period is 1 and duty cycle is 50%, the
+ * result is exactly 12 MHz, which is fine for SGTL5000 MCLK.
+ */
+ pwms = <&pwm4 0 83 0>;
+ };
+
panel: panel {
/* Compatible string is filled in by panel board DT Overlay. */
backlight = <&backlight>;
@@ -82,6 +95,24 @@ reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
vin-supply = <&buck4>;
};
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "SGTL5000-Card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&codec_dai>;
+ simple-audio-card,frame-master = <&codec_dai>;
+ simple-audio-card,widgets = "Headphone", "Headphone Jack";
+ simple-audio-card,routing = "Headphone Jack", "HP_OUT";
+
+ cpu_dai: simple-audio-card,cpu {
+ sound-dai = <&sai3>;
+ };
+
+ codec_dai: simple-audio-card,codec {
+ sound-dai = <&sgtl5000>;
+ };
+ };
+
watchdog { /* TPS3813 */
compatible = "linux,wdt-gpio";
pinctrl-names = "default";
@@ -288,6 +319,15 @@ &i2c1 {
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
+ sgtl5000: audio-codec@a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ #sound-dai-cells = <0>;
+ clocks = <&clk_pwm4>;
+ VDDA-supply = <&buck4>;
+ VDDIO-supply = <&buck4>;
+ };
+
usb-hub@2c {
compatible = "microchip,usb2514bi";
reg = <0x2c>;
@@ -436,6 +476,23 @@ &pwm1 {
status = "disabled";
};
+&pwm4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm4>;
+ status = "okay";
+};
+
+&sai3 {
+ #clock-cells = <0>;
+ #sound-dai-cells = <0>;
+ assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
+ assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
+ assigned-clock-rates = <12288000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai3>;
+ status = "okay";
+};
+
/* SD slot */
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
@@ -785,6 +842,12 @@ MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40000090
>;
};
+ pinctrl_pwm4: pwm4-grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT 0xd6
+ >;
+ };
+
pinctrl_rtc: rtc-grp {
fsl,pins = <
/* RTC_IRQ# */
@@ -816,7 +879,6 @@ pinctrl_sai3: sai3-grp {
MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6
MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6
MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6
- MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6
MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6
>;
};
Add SAI I2S and audio bindings to Data Modul i.MX8M Plus eDM SBC. The SGTL5000 is attached to SAI3, however the SGTL5000 codec MCLK must be supplied even if the SAI3 is not in use and is controlled separately by the codec. The MCLK is also used to drive the codec I2C block, so without MCLK, I2C access to the codec would not be possible. To provide such flexible MCLK control, use PWM4 with period 1 and duty cycle 50% as 12 MHz clock source, as there is no direct way to route MX8MP CCM clock to the MCLK pin. Use codec as bitclock and frame clock master, so that the SGTL5000 PLL can be used to generate derived clock. Signed-off-by: Marek Vasut <marex@denx.de> --- Cc: Conor Dooley <conor+dt@kernel.org> Cc: Fabio Estevam <festevam@gmail.com> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: Rob Herring <robh+dt@kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Shawn Guo <shawnguo@kernel.org> Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org --- V2: Reorder DT properties --- .../freescale/imx8mp-data-modul-edm-sbc.dts | 64 ++++++++++++++++++- 1 file changed, 63 insertions(+), 1 deletion(-)