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Tue, 06 Feb 2024 06:38:01 -0800 (PST) From: Markus Schneider-Pargmann To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Srinivas Kandagatla , Santosh Shilimkar Cc: Andrew Davis , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Markus Schneider-Pargmann Subject: [PATCH 4/4] arm64: dts: ti: k3-am62-wakeup: Add chip efuse nodes Date: Tue, 6 Feb 2024 15:37:11 +0100 Message-ID: <20240206143711.2410135-5-msp@baylibre.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240206143711.2410135-1-msp@baylibre.com> References: <20240206143711.2410135-1-msp@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240206_063803_693095_86AF07B7 X-CRM114-Status: GOOD ( 10.82 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add efuse nodes describing chip variant and speed grade. Signed-off-by: Markus Schneider-Pargmann --- arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi | 36 +++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi index fef76f52a52e..14419df43624 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi @@ -14,10 +14,44 @@ wkup_conf: syscon@43000000 { #size-cells = <1>; ranges = <0x0 0x00 0x43000000 0x20000>; + wkup_efuse: efuse@0 { + compatible = "socionext,uniphier-efuse"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x200>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + chip_manufacturer: jtagidmfg@14 { + reg = <0x14 0x2>; + bits = <1 11>; + }; + + chip_partno: jtagidpartno@15 { + reg = <0x15 0x3>; + bits = <4 16>; + }; + + chip_variant: jtagidvariant@17 { + reg = <0x17 0x1>; + bits = <4 4>; + }; + + chip_speed: jtaguseridspeed@18 { + reg = <0x18 0x4>; + bits = <6 5>; + }; + }; + }; + chipid: chipid@14 { bootph-all; compatible = "ti,am654-chipid"; - reg = <0x14 0x4>; + nvmem-cells = <&chip_variant>, <&chip_partno>, <&chip_manufacturer>; + nvmem-cell-names = "chipvariant", "chippartno", "chipmanufacturer"; }; };