From patchwork Mon Feb 12 14:03:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 13553312 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3A900C48297 for ; Mon, 12 Feb 2024 14:04:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=XCB+4mhgW/91MPJXNOQshRxTCAhbquzDeL9vju1g+PM=; b=MJdt5aOBz5czH1 /SyV2bozhjFfdUPpd+RHeaxjXpi55kFpwbYLK8VZ5Tvj4qFC8henibL2ysiAInMZ5UqgPUJ3szJOe Qtt1Whne5tGKRg/fFSbELpcPX4OamP7CKrr0ZwVSgZ6u5p0e3Wc5wvcx3d5kqiG3JOIqYbvUyVGBA 6BY7fIc15QlBfjTMNDv7b8kE8Qv+JpjMBiIf/9b/lDH5wPu/9GMPNz8d9W9WCM13EnchEpbla/XNF jW1ZYBRhq3Lm2/z1KRFXIjZ+JESlQGVGjjBKZNmCRKTw/q/g1L7do/QFlsibjqyUwxEPlv6VwhCIl I5g2y6ZqnjEEwSLAjb6w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rZWuc-00000005gom-2dxG; Mon, 12 Feb 2024 14:03:58 +0000 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rZWuT-00000005gjN-3fjb for linux-arm-kernel@lists.infradead.org; Mon, 12 Feb 2024 14:03:51 +0000 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-410cb93185dso8025265e9.3 for ; Mon, 12 Feb 2024 06:03:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1707746628; x=1708351428; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3UCCMmhJgpPZWbOVTAspr0xjn11XvYuA37qXyTRrUkA=; b=Eaqsy0XxXX3eLanJnoZ+t+n0JftKBGbV654LAJG8ylh+JvizE1BGOYKE4DhnN/XzwN qiuwq6AyjPYHNfccw3xoGKMxKPplYDAhRtIDOjFs39tENtxjfeRoX5f8VbHw9FKfiKMF Bp119/7JYeJizoRr30MHMCOYLXgwW7lspM/hQdVHpGF9UOhZwFmgwmJYp2aY5nIb3Des bfITsfsb760Aa47qlkala+za9gQoTmV1j8kMmYj+gN2ZzQnGnK19YYNhMB3cQJjxt9yu 4Fgmtj5lkbOZAg6a9W3p9/+eFKh44FB0OSztwc+X6+UuCdWEu+0blrVCLKlEXWLg9ALD uj6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1707746628; x=1708351428; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3UCCMmhJgpPZWbOVTAspr0xjn11XvYuA37qXyTRrUkA=; b=aUn8rh+3+x3n2aTKCloqQAzvc0g6ivPKumpF7buVujXVHJjXx3cJm54TERx24I/PtT z90WzQ70nxxJV+0Uv5smalPAc84hR1WtLWU8PQFwXrr1Weqmdw1swjVVH33FfSmP20G/ w/7mN2XEEZvoNR5JNAvPpzuwt6av9B0UZuBNbUIb1n7qzONY869D7jVe1/gbiBhZUuPw rsn2h9tvnXC5lBbV3ruovSlS3tN2tNfOxO9gzX/RUDwTIK4lczkTBpzAw8P/cxOcdwvf 7KjW5MbFVqVHxOGsliHuHqodpJXywSkNQwvmbVNJRSsoF1+kLbnXN88oaFH06bjMOnyr oLoQ== X-Gm-Message-State: AOJu0YyEtiN38M3GwVRKteNaOmiN1TiVbuuWiHGCWI4uSyxBXmNE8qMT ijWKkVQGcYRrLBgmHpGK+IqV6wdnV342a+rewLIZTWN9iDLn0eWzsKRvZHw9sBY= X-Google-Smtp-Source: AGHT+IEbgvEBoNsAAurtTPnlKh4JR2ymVdbJyrcqUbYPKpD5rJLJU2A7G18SpNCuqft7xJ2hDbxuJA== X-Received: by 2002:adf:f310:0:b0:33b:61fe:a82c with SMTP id i16-20020adff310000000b0033b61fea82cmr4826795wro.22.1707746628063; Mon, 12 Feb 2024 06:03:48 -0800 (PST) X-Forwarded-Encrypted: i=1; AJvYcCXuLucAHTrEw+q2t/r1JV8J5Ne2rVDTnTBWpBXSM//xeorclRlGyHik+CjdLQ+lA/2E90iDoAoJtwXTNht5wZa91kkgVUs5LNT747vZh5T8qUfBN3OUekLf2XaKSBHI9hXl1P/gLPf5rSIuKHE/fR1lJW+mKdVzo5nYN829ZClryn2TdsgC41oZzGqk7lH8+Qgu4z2FlMt5nK1AfEjLSyTg/DGlahPpE0EJAv3p2WaP8yrfHRzQ77PuloAZlz8ezS+PK5qiLWQm9PMz0pp2ju9Om0uE1HoHhvze2DpJPUFpeokYF88baooKjlYYHJkvIEpF66Pcejr8jx87p/gn0ch52PgF4w1TW8o8iN6XCnhScyPuIePsT/bUyh6hIqa+1UrUzlDB2okQlmi46s8H680dio62m8zm/QAUuj5ykx28LYrNm0jfrVUQFjS3isaCBqzybb+z+W159gszHEUoKTBQeNG0WUgAYaUXnOkZkAULTvUeD9mta29b3jKus30pw+QqkKGq4cI83YIwkr5i5/mSkE5DdZ+KF/dJLt/3CjXX1dWZKQTtkrbAfl22/tmgUNrlcjv2u43PGCEoqa50HM4L8DlSROR06m5Vr56xNmez+puEJqA= Received: from ta2.c.googlers.com.com (105.168.195.35.bc.googleusercontent.com. [35.195.168.105]) by smtp.gmail.com with ESMTPSA id v9-20020a5d4b09000000b0033b843786e1sm2135356wrq.51.2024.02.12.06.03.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Feb 2024 06:03:47 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, robh@kernel.org, andi.shyti@kernel.org, krzysztof.kozlowski@linaro.org, semen.protsenko@linaro.org, conor+dt@kernel.org Cc: alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, devicetree@vger.kernel.org, arnd@arndb.de, Tudor Ambarus Subject: [PATCH v2 03/12] spi: s3c64xx: allow full FIFO masks Date: Mon, 12 Feb 2024 14:03:22 +0000 Message-ID: <20240212140331.915498-4-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240212140331.915498-1-tudor.ambarus@linaro.org> References: <20240212140331.915498-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240212_060349_968893_557D1ABC X-CRM114-Status: GOOD ( 18.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The driver is wrong because is using partial register field masks for the SPI_STATUS.{RX, TX}_FIFO_LVL register fields. We see s3c64xx_spi_port_config.fifo_lvl_mask with different values for different instances of the same IP. Take s5pv210_spi_port_config for example, it defines: .fifo_lvl_mask = { 0x1ff, 0x7F }, fifo_lvl_mask is used to determine the FIFO depth of the instance of the IP. In this case, the integrator uses a 256 bytes FIFO for the first SPI instance of the IP, and a 64 bytes FIFO for the second instance. While the first mask reflects the SPI_STATUS.{RX, TX}_FIFO_LVL register fields, the second one is two bits short. Using partial field masks is misleading and can hide problems of the driver's logic. Allow platforms to specify the full FIFO mask, regardless of the FIFO depth. Introduce {rx, tx}_fifomask to represent the SPI_STATUS.{RX, TX}_FIFO_LVL register fields. It's a shifted mask defining the field's length and position. We'll be able to deprecate the use of @rx_lvl_offset, as the shift value can be determined from the mask. The existing compatibles shall start using {rx, tx}_fifomask so that they use the full field mask and to avoid shifting the mask to position, and then shifting it back to zero in the {TX, RX}_FIFO_LVL macros. @rx_lvl_offset will be deprecated in a further patch, after we have the infrastructure to deprecate @fifo_lvl_mask as well. No functional change intended. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 40 +++++++++++++++++++++++++++++++++++---- 1 file changed, 36 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 6ff3b25b6feb..338ca3f03ea5 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -3,6 +3,7 @@ // Copyright (c) 2009 Samsung Electronics Co., Ltd. // Jaswinder Singh +#include #include #include #include @@ -109,10 +110,10 @@ #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id]) #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \ (1 << (i)->port_conf->tx_st_done)) ? 1 : 0) -#define TX_FIFO_LVL(v, i) (((v) >> S3C64XX_SPI_ST_TX_FIFO_LVL_SHIFT) & \ - FIFO_LVL_MASK(i)) -#define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \ - FIFO_LVL_MASK(i)) +#define TX_FIFO_LVL(v, sdd) (((v) & (sdd)->tx_fifomask) >> \ + __ffs((sdd)->tx_fifomask)) +#define RX_FIFO_LVL(v, sdd) (((v) & (sdd)->rx_fifomask) >> \ + __ffs((sdd)->rx_fifomask)) #define FIFO_DEPTH(i) ((FIFO_LVL_MASK(i) >> 1) + 1) #define S3C64XX_SPI_MAX_TRAILCNT 0x3ff @@ -136,6 +137,10 @@ struct s3c64xx_spi_dma_data { * struct s3c64xx_spi_port_config - SPI Controller hardware info * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register. * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter. + * @rx_fifomask: SPI_STATUS.RX_FIFO_LVL mask. Shifted mask defining the field's + * length and position. + * @tx_fifomask: SPI_STATUS.TX_FIFO_LVL mask. Shifted mask defining the field's + * length and position. * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter. * @clk_div: Internal clock divider * @quirks: Bitmask of known quirks @@ -154,6 +159,8 @@ struct s3c64xx_spi_dma_data { struct s3c64xx_spi_port_config { int fifo_lvl_mask[MAX_SPI_PORTS]; int rx_lvl_offset; + u32 rx_fifomask; + u32 tx_fifomask; int tx_st_done; int quirks; int clk_div; @@ -184,6 +191,10 @@ struct s3c64xx_spi_port_config { * @tx_dma: Local transmit DMA data (e.g. chan and direction) * @port_conf: Local SPI port configuration data * @port_id: Port identification number + * @rx_fifomask: SPI_STATUS.RX_FIFO_LVL mask. Shifted mask defining the field's + * length and position. + * @tx_fifomask: SPI_STATUS.TX_FIFO_LVL mask. Shifted mask defining the field's + * length and position. */ struct s3c64xx_spi_driver_data { void __iomem *regs; @@ -203,6 +214,8 @@ struct s3c64xx_spi_driver_data { struct s3c64xx_spi_dma_data tx_dma; const struct s3c64xx_spi_port_config *port_conf; unsigned int port_id; + u32 rx_fifomask; + u32 tx_fifomask; }; static void s3c64xx_flush_fifo(struct s3c64xx_spi_driver_data *sdd) @@ -1183,6 +1196,23 @@ static inline const struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config( return (const struct s3c64xx_spi_port_config *)platform_get_device_id(pdev)->driver_data; } +static void s3c64xx_spi_set_fifomask(struct s3c64xx_spi_driver_data *sdd) +{ + const struct s3c64xx_spi_port_config *port_conf = sdd->port_conf; + + if (port_conf->rx_fifomask) + sdd->rx_fifomask = port_conf->rx_fifomask; + else + sdd->rx_fifomask = FIFO_LVL_MASK(sdd) << + port_conf->rx_lvl_offset; + + if (port_conf->tx_fifomask) + sdd->tx_fifomask = port_conf->tx_fifomask; + else + sdd->tx_fifomask = FIFO_LVL_MASK(sdd) << + S3C64XX_SPI_ST_TX_FIFO_LVL_SHIFT; +} + static int s3c64xx_spi_probe(struct platform_device *pdev) { struct resource *mem_res; @@ -1231,6 +1261,8 @@ static int s3c64xx_spi_probe(struct platform_device *pdev) sdd->port_id = pdev->id; } + s3c64xx_spi_set_fifomask(sdd); + sdd->cur_bpw = 8; sdd->tx_dma.direction = DMA_MEM_TO_DEV;