| Message ID | 20240215055159.2440898-1-anshuman.khandual@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64/sysreg: Update ID_AA64DFR0_EL1 and ID_DFR0_EL1 | expand |
On Thu, Feb 15, 2024 at 11:21:59AM +0530, Anshuman Khandual wrote: > This just updates ID_DFR0_EL1.CopDbg and ID_AA64DFR0_EL1.DebugVer register > fields as per the definitions based on DDI0601 2023-12. Just as a general note for non-trival registers it's easier to review if we change one register per patch, it avoids having to re-review the same registers repeatedly and for incremental changes like this it helps with the fact that diff does badly at offering context. > --- a/arch/arm64/tools/sysreg > +++ b/arch/arm64/tools/sysreg > @@ -231,6 +231,7 @@ Enum 3:0 CopDbg > 0b1000 Debugv8p2 > 0b1001 Debugv8p4 > 0b1010 Debugv8p8 > + 0b1011 Debugv8p9 > EndEnum > EndSysreg This is ID_AA64DFR0_EL1 and is missing at least an update to PMSVer. > > @@ -1247,6 +1248,7 @@ UnsignedEnum 3:0 DebugVer > 0b1000 V8P2 > 0b1001 V8P4 > 0b1010 V8P8 > + 0b1011 V8P9 > EndEnum > EndSysreg This is ID_DFR0_EL1 and is missing an update to at least PerfMon.
On 2/15/24 18:30, Mark Brown wrote: > On Thu, Feb 15, 2024 at 11:21:59AM +0530, Anshuman Khandual wrote: > >> This just updates ID_DFR0_EL1.CopDbg and ID_AA64DFR0_EL1.DebugVer register >> fields as per the definitions based on DDI0601 2023-12. > > Just as a general note for non-trival registers it's easier to review if > we change one register per patch, it avoids having to re-review the same > registers repeatedly and for incremental changes like this it helps with > the fact that diff does badly at offering context. Agreed, and noted. > >> --- a/arch/arm64/tools/sysreg >> +++ b/arch/arm64/tools/sysreg >> @@ -231,6 +231,7 @@ Enum 3:0 CopDbg >> 0b1000 Debugv8p2 >> 0b1001 Debugv8p4 >> 0b1010 Debugv8p8 >> + 0b1011 Debugv8p9 >> EndEnum >> EndSysreg > > This is ID_AA64DFR0_EL1 and is missing at least an update to PMSVer. > >> >> @@ -1247,6 +1248,7 @@ UnsignedEnum 3:0 DebugVer >> 0b1000 V8P2 >> 0b1001 V8P4 >> 0b1010 V8P8 >> + 0b1011 V8P9 >> EndEnum >> EndSysreg > > This is ID_DFR0_EL1 and is missing an update to at least PerfMon. Will fold in the following changes i.e for ID_DFR0_EL1 and for ID_AA64DFR0_EL1 respectively and then split the patch into two - one for each register. diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index cc2914d6ebdc..508224a0e078 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -200,6 +200,7 @@ UnsignedEnum 27:24 PerfMon 0b0110 PMUv3p5 0b0111 PMUv3p7 0b1000 PMUv3p8 + 0b1001 PMUv3p9 0b1111 IMPDEF EndEnum Enum 23:20 MProfDbg @@ -1222,6 +1223,7 @@ UnsignedEnum 35:32 PMSVer 0b0010 V1P1 0b0011 V1P2 0b0100 V1P3 + 0b0101 V1P4 EndEnum Field 31:28 CTX_CMPs Res0 27:24
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 4c9b67934367..94692abfeeb9 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -231,6 +231,7 @@ Enum 3:0 CopDbg 0b1000 Debugv8p2 0b1001 Debugv8p4 0b1010 Debugv8p8 + 0b1011 Debugv8p9 EndEnum EndSysreg @@ -1247,6 +1248,7 @@ UnsignedEnum 3:0 DebugVer 0b1000 V8P2 0b1001 V8P4 0b1010 V8P8 + 0b1011 V8P9 EndEnum EndSysreg
This just updates ID_DFR0_EL1.CopDbg and ID_AA64DFR0_EL1.DebugVer register fields as per the definitions based on DDI0601 2023-12. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Mark Brown <broonie@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> --- arch/arm64/tools/sysreg | 2 ++ 1 file changed, 2 insertions(+)