From patchwork Mon Feb 19 15:05:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Xiwen via B4 Relay X-Patchwork-Id: 13562826 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8D461C48BC3 for ; Mon, 19 Feb 2024 15:07:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Reply-To:List-Subscribe:List-Help: List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References: Message-Id:MIME-Version:Subject:Date:From:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=v/8R52cgSHwQQk4llfiH6GDz0FZ6bj3BEYDwewv4yP0=; b=3nDV8vF20LGaR7 9IVfJCC6m/PWqKfWlMRpW2SUT7I3mN2F6/XDUIvnurpJm/vVpLvqTCZoYP3uKCSY+AIGb/OLDkih+ HqKQIWD18o7YZnRLACX/7+9giDqC4UgD/ura8pfxLLp2IdRxSQovceUtIKspbqkK4e2pZ3pAI7THI AlklAz9CV4dpwrlv9T3glqKJNsr3ShJ0VRr8FZM95LnLBO/fCj76yhhMHY9uPNoo9MAZB4+LE34QL tiUWDrlqlk23gzbAhVNySs9eb/ECWRrOYxL1SQSqBmmaNTc2Kee9UwzdAIizEI+cr74n2o1DzyViA UuSyr9sZKxlopW0Vmd3w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rc5Eh-0000000B0lU-2wA3; Mon, 19 Feb 2024 15:07:15 +0000 Received: from sin.source.kernel.org ([145.40.73.55]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rc5EX-0000000B0f6-0AFm for linux-arm-kernel@lists.infradead.org; Mon, 19 Feb 2024 15:07:06 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id F3B06CE12E7; Mon, 19 Feb 2024 15:07:02 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPS id 5E83BC433B1; Mon, 19 Feb 2024 15:07:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1708355221; bh=ZMHx0vXY3BCnqeeGRXitQ/9VWNOaOqi09FTpVeOGZiU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=dGIJ8r5vC/Wom7KdLtQbklUS/MgZliqOr/U2dp4sUTRNlGJnsukNQJpAtFMWtab2P 54jojOTACU+x7Tzi+fU92Lj/pgKXs29YflQ4N0nNeiyoKC6/2sIOwin/xvHsg56UUO uNZ+IjhqhZCcqEucwoAIBwH0zJs0sZqMu8jZtc8IQCTmfPySsOibgCo92Qcy0v8k9X V/cMqJNIsUp0UjtsOSV1vdDnkwKsso+ab1rN3gPctQEyFxyYNVPLnoTskMZkRGAfhS kUDgEkbRiHRs7Edceu/bcRulUtxNEMGD70NeqXD4ZPIDJBskMY/oN6mxSViG78VrH8 fUu8PiHdqM+fQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41B41C54788; Mon, 19 Feb 2024 15:07:01 +0000 (UTC) From: Yang Xiwen via B4 Relay Date: Mon, 19 Feb 2024 23:05:28 +0800 Subject: [PATCH v3 3/3] arm64: dts: hi3798cv200: add cache info MIME-Version: 1.0 Message-Id: <20240219-cache-v3-3-a33c57534ae9@outlook.com> References: <20240219-cache-v3-0-a33c57534ae9@outlook.com> In-Reply-To: <20240219-cache-v3-0-a33c57534ae9@outlook.com> To: Wei Xu , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jiancheng Xue , Alex Elder , Peter Griffin Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org, Yang Xiwen X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1708355220; l=2828; i=forbidden405@outlook.com; s=20230724; h=from:subject:message-id; bh=JCsSJLmRtX8xpTr7tVRxOMtB1SM8sQgXyZwjBU7p06U=; b=xqgpLfoVrqGs2VoZ+PuH1dOy0Z9Fq4MUu+Y3kHKp1cEtduRNLeydUq8AxTXjj8so/JunkHLKW Q8mtsMytX5+DXoRi5eQY8ceAPKRU3PIgKKnWzdSWoZKfDdtYhrLPDqF X-Developer-Key: i=forbidden405@outlook.com; a=ed25519; pk=qOD5jhp891/Xzc+H/PZ8LWVSWE3O/XCQnAg+5vdU2IU= X-Endpoint-Received: by B4 Relay for forbidden405@outlook.com/20230724 with auth_id=67 X-Original-From: Yang Xiwen X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240219_070705_672753_BAF4DD02 X-CRM114-Status: GOOD ( 11.18 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: forbidden405@outlook.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Yang Xiwen During boot, the kernel complains: [ 0.044029] cacheinfo: Unable to detect cache hierarchy for CPU 0 So add L1/L2 cache info to the dts according to the datasheet. (32KiB L1 i-cache + 32 KiB L1 d-cache + 512 KiB L2 unified cache) With this patch, the line above is gone and the following info is added to the output of `lscpu`: Caches (sum of all): L1d: 128 KiB (4 instances) L1i: 128 KiB (4 instances) L2: 512 KiB (1 instance) Fixes: 2f20182ed670 ("arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board") Signed-off-by: Yang Xiwen Cc: stable@vger.kernel.org --- arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 37 ++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index fc64d2fa99eb..f6bc001c3832 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -31,6 +31,13 @@ cpu@0 { device_type = "cpu"; reg = <0x0 0x0>; enable-method = "psci"; + d-cache-size = <0x8000>; /* 32 KiB */ + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0x8000>; /* 32 KiB */ + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&L2>; }; cpu@1 { @@ -38,6 +45,13 @@ cpu@1 { device_type = "cpu"; reg = <0x0 0x1>; enable-method = "psci"; + d-cache-size = <0x8000>; /* 32 KiB */ + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0x8000>; /* 32 KiB */ + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&L2>; }; cpu@2 { @@ -45,6 +59,13 @@ cpu@2 { device_type = "cpu"; reg = <0x0 0x2>; enable-method = "psci"; + d-cache-size = <0x8000>; /* 32 KiB */ + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0x8000>; /* 32 KiB */ + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&L2>; }; cpu@3 { @@ -52,9 +73,25 @@ cpu@3 { device_type = "cpu"; reg = <0x0 0x3>; enable-method = "psci"; + d-cache-size = <0x8000>; /* 32 KiB */ + d-cache-line-size = <64>; + d-cache-sets = <128>; + i-cache-size = <0x8000>; /* 32 KiB */ + i-cache-line-size = <64>; + i-cache-sets = <256>; + next-level-cache = <&L2>; }; }; + L2: l2-cache { + compatible = "cache"; + cache-unified; + cache-size = <0x80000>; /* 512 KiB */ + cache-line-size = <64>; + cache-sets = <512>; + cache-level = <2>; + }; + gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */