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Tue, 20 Feb 2024 00:18:13 -0600 Received: from localhost (jluthra.dhcp.ti.com [172.24.227.217]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 41K6ICk7120873; Tue, 20 Feb 2024 00:18:12 -0600 From: Jai Luthra Date: Tue, 20 Feb 2024 11:48:02 +0530 Subject: [PATCH v2 1/4] arm64: dts: ti: k3-am62p: Fix memory ranges for DMSS MIME-Version: 1.0 Message-ID: <20240220-am62p_csi-v2-1-3e71d9945571@ti.com> References: <20240220-am62p_csi-v2-0-3e71d9945571@ti.com> In-Reply-To: <20240220-am62p_csi-v2-0-3e71d9945571@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Davis , Bryan Brattlof , Dhruva Gole CC: , , , Vaishnav Achath , Devarsh Thakkar , Aradhya Bhatia , Jai Luthra X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1338; i=j-luthra@ti.com; h=from:subject:message-id; bh=KAReUPQx9gvzzba47vWWOb5Oekj/PePm9BhH+eG3XlQ=; b=owEBbQKS/ZANAwAIAUPekfkkmnFFAcsmYgBl1EQe/ATjXPVYP4orc1Clk5F32f+sFPV2jgia0 Tcj9gDbT5OJAjMEAAEIAB0WIQRN4NgY5dV16NRar8VD3pH5JJpxRQUCZdREHgAKCRBD3pH5JJpx Rf64EADLqMiQyJqkDRSyqQnnu9j0mVc9kq1MLa7jJCtJqo5fMPjsb9Uh9E9iGj3niqaA1OMZGJQ HY82Ts4C39y+9qmW7ktWjs44NduqQEjpNgIl+8qOolFboOlmChh1H7ibHgdo7nCNfE52BSsuhT2 c2cbcLATqWp9rLmrgd6NxgD1n+F9GodVuzmHCXaYJMVDikiCcFCuu6ZkBABsmIDMUPj+/3cf5jU Ot3lAB8zJCeE6JE0gbkxqFHfweEJX52luMXCxWpvZSwPTs3Dy4/sUY01lKKjh32K2s9sruXGhNm gCNXKRUod/xmKa4AurGPwX+Mk+blfoVjP1uwNxgV1IhduHZ4gjvZVi+3DWevG+4/zjP2UmOkZvD 7WKRMID5pLSlVeIaNnQ0OsjG65cBVLtgeQiltoRStavUXtWOnDjXLyOFsqfKNPixfus4t2EcXE0 TI5YWXW5zcp/3JN7hlFkPPRkSLgGVPX57YZ+qfccJq7bFIrJfDIw5u136szYJUaC6PI9UuNdsoo oP24PAVcGr1+UhVF5hmauDNebOyDNQ0FBZHgpO0UU2P83+BoEbVtxuhgjrafsGPpJU18q8gYu6m ycOh5oN+kCa1CwA/z3fIDFM5zNuH5nazw4rcg6tzkyOk0w8w4KZEmVl23hGUKd7kOrz+RlI2Kl3 x8GD+UI5nDNhFiQ== X-Developer-Key: i=j-luthra@ti.com; a=openpgp; fpr=4DE0D818E5D575E8D45AAFC543DE91F9249A7145 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240219_221823_755317_CA621537 X-CRM114-Status: GOOD ( 10.84 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The INTR module for DMASS1 (CSI specific DMASS) is outside the currently available ranges, as it starts at 0x4e400000. So fix the ranges property to enable programming the interrupts correctly. Fixes: 29075cc09f43 ("arm64: dts: ti: Introduce AM62P5 family of SoCs") Reviewed-by: Vaishnav Achath Signed-off-by: Jai Luthra --- arch/arm64/boot/dts/ti/k3-am62p.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p.dtsi b/arch/arm64/boot/dts/ti/k3-am62p.dtsi index d111e044bfdf..94babc412575 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p.dtsi @@ -71,7 +71,7 @@ cbass_main: bus@f0000 { <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */ <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */ - <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */ + <0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */ <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */ <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */ <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */