From patchwork Wed Feb 21 05:35:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikandan Muralidharan X-Patchwork-Id: 13564948 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 08869C48BF6 for ; Wed, 21 Feb 2024 05:37:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=dQ9E/QoXg2muwmEkS7Xz7jQwEhbPVl383Tvb1PYACAc=; b=W8gxi6wdLSFKLA vobtWN9PF01Vrvlvql83Cc+PjJE67X2YW2n+G72R0Zs1hROqTTkDMbqT12cH8r8Tb1L76GJzQwBIu gvcPMyZqfqvI4rr33iiHb0SIpLs09fWdTxoTkU/5SHQ+Z1Osh/JfMZ9hkAqfQRh/Y7Amk/fUkB2T0 eu/d2Lo8OZKz2kfyeXG2kTzDaKId0hdJhtrgY8JMO7Q7gr6T2+Vkg1OR+GT7QJN/DLQItXwAy+i+o LSPIyunv4nu87QSkVsW7frCzOlbqXYzDzwjfU+FhBlWQ4lM3DFAkLAQ2BjKf+708Q9Isg74ao2NOj TshP7g1ZlnWSsq7dBrpQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rcfIA-0000000HDny-0Ean; Wed, 21 Feb 2024 05:37:14 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rcfHp-0000000HDQ5-1qmN for linux-arm-kernel@lists.infradead.org; Wed, 21 Feb 2024 05:37:01 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1708493813; x=1740029813; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=OKLm0TpKtjMzC5zoHct+zFILT4roGx2dwy6wf/eZcDs=; b=ESsPKxh90v3IebAWMkdHoMdZzpJP43h5GLWjHzshyhDE2ocwe0CaexBj rK63ml8vTQu9kBIZ1ZVHcfE0zzI8JMkvlX4rmU8XjEYZuyIVxnS/IbO+Q CvbIQK0Wo8TBHf3DElPzDaeGj+XVJcjEpHYg2JWtBujmLJvfES0gFxyX1 X+UICizZtG3GYAQakxUirol/ifAp9K5ND3DWKwWBMRkL+jKafbSy5jtXj X34ZSZeyHRIWlYeIVmnc8WWwAlvLVhTgeLi+kHqym99V255acDziJYDEv E4nT8N69ya9UhNzY2vJ1QZo3P7iXTOuRUnPelcjBkUaeeoLfLjUrBGcq8 w==; X-CSE-ConnectionGUID: uvmqqrvDTHSClXFWxIq5Hw== X-CSE-MsgGUID: 5l/51w8DQXOZuaIoCZ2aBg== X-IronPort-AV: E=Sophos;i="6.06,174,1705388400"; d="scan'208";a="183844466" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Feb 2024 22:36:47 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 20 Feb 2024 22:36:43 -0700 Received: from che-lt-i67131.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Tue, 20 Feb 2024 22:36:35 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v8 7/7] drm: atmel-hlcdc: add LCD controller layer definition for sam9x75 Date: Wed, 21 Feb 2024 11:05:31 +0530 Message-ID: <20240221053531.12701-8-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240221053531.12701-1-manikandan.m@microchip.com> References: <20240221053531.12701-1-manikandan.m@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240220_213653_762104_35CF5EAE X-CRM114-Status: UNSURE ( 9.97 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the LCD controller layer definition and descriptor structure for sam9x75 for the following layers: - Base Layer - Overlay1 Layer - Overlay2 Layer - High End Overlay Signed-off-by: Manikandan Muralidharan --- drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c | 100 +++++++++++++++++++ 1 file changed, 100 insertions(+) diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c index b09df821cbc0..9ce429f889ca 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c @@ -467,6 +467,102 @@ static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sam9x60 = { .ops = &atmel_hlcdc_ops, }; +static const struct atmel_hlcdc_layer_desc atmel_xlcdc_sam9x75_layers[] = { + { + .name = "base", + .formats = &atmel_hlcdc_plane_rgb_formats, + .regs_offset = 0x60, + .id = 0, + .type = ATMEL_HLCDC_BASE_LAYER, + .cfgs_offset = 0x1c, + .layout = { + .xstride = { 2 }, + .default_color = 3, + .general_config = 4, + .disc_pos = 5, + .disc_size = 6, + }, + .clut_offset = 0x700, + }, + { + .name = "overlay1", + .formats = &atmel_hlcdc_plane_rgb_formats, + .regs_offset = 0x160, + .id = 1, + .type = ATMEL_HLCDC_OVERLAY_LAYER, + .cfgs_offset = 0x1c, + .layout = { + .pos = 2, + .size = 3, + .xstride = { 4 }, + .pstride = { 5 }, + .default_color = 6, + .chroma_key = 7, + .chroma_key_mask = 8, + .general_config = 9, + }, + .clut_offset = 0xb00, + }, + { + .name = "overlay2", + .formats = &atmel_hlcdc_plane_rgb_formats, + .regs_offset = 0x260, + .id = 2, + .type = ATMEL_HLCDC_OVERLAY_LAYER, + .cfgs_offset = 0x1c, + .layout = { + .pos = 2, + .size = 3, + .xstride = { 4 }, + .pstride = { 5 }, + .default_color = 6, + .chroma_key = 7, + .chroma_key_mask = 8, + .general_config = 9, + }, + .clut_offset = 0xf00, + }, + { + .name = "high-end-overlay", + .formats = &atmel_hlcdc_plane_rgb_and_yuv_formats, + .regs_offset = 0x360, + .id = 3, + .type = ATMEL_HLCDC_OVERLAY_LAYER, + .cfgs_offset = 0x30, + .layout = { + .pos = 2, + .size = 3, + .memsize = 4, + .xstride = { 5, 7 }, + .pstride = { 6, 8 }, + .default_color = 9, + .chroma_key = 10, + .chroma_key_mask = 11, + .general_config = 12, + .csc = 16, + .scaler_config = 23, + .vxs_config = 30, + .hxs_config = 31, + }, + .clut_offset = 0x1300, + }, +}; + +static const struct atmel_hlcdc_dc_desc atmel_xlcdc_dc_sam9x75 = { + .min_width = 0, + .min_height = 0, + .max_width = 2048, + .max_height = 2048, + .max_spw = 0x3ff, + .max_vpw = 0x3ff, + .max_hpw = 0x3ff, + .fixed_clksrc = true, + .is_xlcdc = true, + .nlayers = ARRAY_SIZE(atmel_xlcdc_sam9x75_layers), + .layers = atmel_xlcdc_sam9x75_layers, + .ops = &atmel_xlcdc_ops, +}; + static const struct of_device_id atmel_hlcdc_of_match[] = { { .compatible = "atmel,at91sam9n12-hlcdc", @@ -492,6 +588,10 @@ static const struct of_device_id atmel_hlcdc_of_match[] = { .compatible = "microchip,sam9x60-hlcdc", .data = &atmel_hlcdc_dc_sam9x60, }, + { + .compatible = "microchip,sam9x75-xlcdc", + .data = &atmel_xlcdc_dc_sam9x75, + }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, atmel_hlcdc_of_match);