From patchwork Fri Feb 23 12:36:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Raphael Gallais-Pou X-Patchwork-Id: 13569018 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 97A8DC5478C for ; Fri, 23 Feb 2024 12:40:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:CC:To:In-Reply-To:References:Message-ID :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=bDondUI1k0McjiCtj4X8K6Ss0cNAEA3XVmuJLj5mIkk=; b=ITi7yLCzYhBGha MUPme4WqfNJz12HBnUb4wsl/xHJ8YrLMve2hCsE9U99YC3HnuGtxsriKIbpJyXvKxtErQgeXKWWLG 5K50eJNFuL8VnyyRl13KBnEDKlN9LkYfA8PdOYnUHUKGkFXjbq+mreHEo2zXI4fURbqpjX65c6YY/ DWw0sml21uO4a2Mczdw2BNyfPg1e8pwqSGmZesaoTE3t7Z0V5/dd6L5sHrKUjsBIbpIK7CcsEgpF0 JjikLxWAIlWPmgYrSVL/ul+X54YU+kumbzItpjkiPevxdy8iQsHHvWALmmShD86X0jk0T6x7WwxR6 MDs+BsdY72p3aDX3KFBw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rdUpj-00000009NIu-1GLz; Fri, 23 Feb 2024 12:39:24 +0000 Received: from mx08-00178001.pphosted.com ([91.207.212.93]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rdUou-00000009N40-2eOp for linux-arm-kernel@lists.infradead.org; Fri, 23 Feb 2024 12:38:43 +0000 Received: from pps.filterd (m0369457.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 41NCY4S5025859; Fri, 23 Feb 2024 13:38:14 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:date:subject:mime-version:content-type :content-transfer-encoding:message-id:references:in-reply-to:to :cc; s=selector1; bh=0b38tedRyxz1wugMy9qAGe9nstQPcZ6cdawHN0/CbEE =; b=5DlHXVC/1Yh3OzXErhk6+W89uuSLf/ldw8IF1vqPYQiHck722Nkupz4lOFQ tsbopW4ajlyBeqQ5xyhg1RqtjU2EGfdlip7o6j3vgNvsaoIRp1yvIB8FOQrinfUa l+xERL6AH/MnC8qrBPqR+VwA/U2OtcHZgJUKPdPcPiosidge2Z2HBDftqpz0E1HU U8VXIjbdq3WY/+mVFDlhBFjivpzKr7cIGoof2FbIfUtcfXVZK8XEvMPY3fCDV9yq X3XJN+XrFNGkKPZ0jVkpBynvZy2z1wd+xWG+JBhXy8ctCrJRizKiG2HQOjJ+zQBy cbBHpOxKNDdcTfrGa0aEGZ2+xsA== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3wd2024nv7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 23 Feb 2024 13:38:13 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 7383D40047; Fri, 23 Feb 2024 13:38:05 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id B09F628DDC5; Fri, 23 Feb 2024 13:36:55 +0100 (CET) Received: from localhost (10.129.178.151) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Fri, 23 Feb 2024 13:36:53 +0100 From: Raphael Gallais-Pou Date: Fri, 23 Feb 2024 13:36:48 +0100 Subject: [PATCH v3 1/4] ARM: dts: stm32: add LTDC support for STM32MP13x SoC family MIME-Version: 1.0 Message-ID: <20240223-ltdc_mp13-v3-1-7f92a59ca11f@foss.st.com> References: <20240223-ltdc_mp13-v3-0-7f92a59ca11f@foss.st.com> In-Reply-To: <20240223-ltdc_mp13-v3-0-7f92a59ca11f@foss.st.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Neil Armstrong , Jessica Zhang , Sam Ravnborg , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter CC: , , , , , Raphael Gallais-Pou , Yannick Fertre X-Mailer: b4 0.12.4 X-Originating-IP: [10.129.178.151] X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-22_15,2024-02-23_01,2023-05-22_02 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240223_043840_461329_01454429 X-CRM114-Status: GOOD ( 10.10 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org STM32MP13x SoC family embeds a new version of LTDC (Liquid crystal display - Thin film transistor) Display Controller. It provides a parallel digital RGB (red, green, blue) and signals for horizontal, vertical synchronization, pixel clock and data enable as output to interface directly to a variety of LCD-TFT panels. Main features * 2 input layers blended together to compose the display * Cropping of layers from any input size and location * Multiple input pixel formats: – Predefined ARGB, with 7 formats: ARGB8888, ABGR8888, RGBA8888, BGRA8888, RGB565, BGR565, RGB888packed. – Flexible ARGB, allowing any width and location for A,R,G,B components. – Predefined YUV, with 3 formats: YUV422-1L (FourCC: YUYV, Interleaved), YUV420-2L (FourCC: NV12, semi planar), YUV420-3L (FourCC: Yxx, full planar) with some flexibility on the sequence of the component. * Color look-up table (CLUT) up to 256 colors (256x24 bits) per layer * Color transparency keying * Composition with flexible window position and size versus output display * Blending with flexible layer order and alpha value (per pixel or constant) * Background underlying color * Gamma with non-linear configurable table * Dithering for output with less bits per component (pseudo-random on 2 bits) * Polarity inversion for HSync, VSync, and DataEnable outputs * Output as RGB888 24 bpp or YUV422 16 bpp * Secure layer (using Layer2) capability, with grouped regs and additional interrupt set * Interrupts based on 7 different events * AXI master interface with long efficient bursts (64 or 128 bytes) Signed-off-by: Raphael Gallais-Pou Signed-off-by: Yannick Fertre --- arch/arm/boot/dts/st/stm32mp135.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp135.dtsi b/arch/arm/boot/dts/st/stm32mp135.dtsi index 68d32f9f5314..834a4d545fe4 100644 --- a/arch/arm/boot/dts/st/stm32mp135.dtsi +++ b/arch/arm/boot/dts/st/stm32mp135.dtsi @@ -19,5 +19,16 @@ dcmipp: dcmipp@5a000000 { port { }; }; + + ltdc: display-controller@5a001000 { + compatible = "st,stm32-ltdc"; + reg = <0x5a001000 0x400>; + interrupts = , + ; + clocks = <&rcc LTDC_PX>; + clock-names = "lcd"; + resets = <&scmi_reset RST_SCMI_LTDC>; + status = "disabled"; + }; }; };