| Message ID | 20240229083431.356578-1-anshuman.khandual@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [V2] arm64/hw_breakpoint: Directly use ESR_ELx_WNR for an watchpoint exception | expand |
On Thu, Feb 29, 2024 at 02:04:31PM +0530, Anshuman Khandual wrote: > Let's use existing ISS encoding for an watchpoint exception i.e ESR_ELx_WNR > This represents an instruction's either writing to or reading from a memory > location during an watchpoint exception. While here this drops non-standard > macro AARCH64_ESR_ACCESS_MASK. > > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will@kernel.org> > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > Reviewed-by: Mark Brown <broonie@kernel.org> > Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> This looks like a sensible cleanup, so: Acked-by: Mark Rutland <mark.rutland@arm.com> Mark. > --- > This applies on v6.8-rc5 > > Changes in V2: > > - Dropped new ISS encoding details ESR_ELx_WnR and ESR_ELx_WnR_SHIFT > - Directly used existing ESR_ELx_WNR per Catalin > - Updated the commit message as required > > Changes in V1: > > https://lore.kernel.org/all/20240223094615.3977323-1-anshuman.khandual@arm.com/ > > arch/arm64/include/asm/hw_breakpoint.h | 1 - > arch/arm64/kernel/hw_breakpoint.c | 3 ++- > 2 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/include/asm/hw_breakpoint.h b/arch/arm64/include/asm/hw_breakpoint.h > index 84055329cd8b..bd81cf17744a 100644 > --- a/arch/arm64/include/asm/hw_breakpoint.h > +++ b/arch/arm64/include/asm/hw_breakpoint.h > @@ -59,7 +59,6 @@ static inline void decode_ctrl_reg(u32 reg, > /* Watchpoints */ > #define ARM_BREAKPOINT_LOAD 1 > #define ARM_BREAKPOINT_STORE 2 > -#define AARCH64_ESR_ACCESS_MASK (1 << 6) > > /* Lengths */ > #define ARM_BREAKPOINT_LEN_1 0x1 > diff --git a/arch/arm64/kernel/hw_breakpoint.c b/arch/arm64/kernel/hw_breakpoint.c > index 35225632d70a..2f5755192c2b 100644 > --- a/arch/arm64/kernel/hw_breakpoint.c > +++ b/arch/arm64/kernel/hw_breakpoint.c > @@ -21,6 +21,7 @@ > > #include <asm/current.h> > #include <asm/debug-monitors.h> > +#include <asm/esr.h> > #include <asm/hw_breakpoint.h> > #include <asm/traps.h> > #include <asm/cputype.h> > @@ -779,7 +780,7 @@ static int watchpoint_handler(unsigned long addr, unsigned long esr, > * Check that the access type matches. > * 0 => load, otherwise => store > */ > - access = (esr & AARCH64_ESR_ACCESS_MASK) ? HW_BREAKPOINT_W : > + access = (esr & ESR_ELx_WNR) ? HW_BREAKPOINT_W : > HW_BREAKPOINT_R; > if (!(access & hw_breakpoint_type(wp))) > continue; > -- > 2.25.1 >
On Thu, Feb 29, 2024 at 02:04:31PM +0530, Anshuman Khandual wrote: > Let's use existing ISS encoding for an watchpoint exception i.e ESR_ELx_WNR > This represents an instruction's either writing to or reading from a memory > location during an watchpoint exception. While here this drops non-standard > macro AARCH64_ESR_ACCESS_MASK. Reviewed-by: Mark Brown <broonie@kernel.org>
On Thu, 29 Feb 2024 14:04:31 +0530, Anshuman Khandual wrote: > Let's use existing ISS encoding for an watchpoint exception i.e ESR_ELx_WNR > This represents an instruction's either writing to or reading from a memory > location during an watchpoint exception. While here this drops non-standard > macro AARCH64_ESR_ACCESS_MASK. > > Applied to arm64 (for-next/misc), thanks! [1/1] arm64/hw_breakpoint: Directly use ESR_ELx_WNR for an watchpoint exception https://git.kernel.org/arm64/c/9d6b6789c878
diff --git a/arch/arm64/include/asm/hw_breakpoint.h b/arch/arm64/include/asm/hw_breakpoint.h index 84055329cd8b..bd81cf17744a 100644 --- a/arch/arm64/include/asm/hw_breakpoint.h +++ b/arch/arm64/include/asm/hw_breakpoint.h @@ -59,7 +59,6 @@ static inline void decode_ctrl_reg(u32 reg, /* Watchpoints */ #define ARM_BREAKPOINT_LOAD 1 #define ARM_BREAKPOINT_STORE 2 -#define AARCH64_ESR_ACCESS_MASK (1 << 6) /* Lengths */ #define ARM_BREAKPOINT_LEN_1 0x1 diff --git a/arch/arm64/kernel/hw_breakpoint.c b/arch/arm64/kernel/hw_breakpoint.c index 35225632d70a..2f5755192c2b 100644 --- a/arch/arm64/kernel/hw_breakpoint.c +++ b/arch/arm64/kernel/hw_breakpoint.c @@ -21,6 +21,7 @@ #include <asm/current.h> #include <asm/debug-monitors.h> +#include <asm/esr.h> #include <asm/hw_breakpoint.h> #include <asm/traps.h> #include <asm/cputype.h> @@ -779,7 +780,7 @@ static int watchpoint_handler(unsigned long addr, unsigned long esr, * Check that the access type matches. * 0 => load, otherwise => store */ - access = (esr & AARCH64_ESR_ACCESS_MASK) ? HW_BREAKPOINT_W : + access = (esr & ESR_ELx_WNR) ? HW_BREAKPOINT_W : HW_BREAKPOINT_R; if (!(access & hw_breakpoint_type(wp))) continue;