| Message ID | 20240229233556.116944-1-aford173@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/2] arm64: dts: imx8mp-beacon-kit: Move sai3 to Audio_PLL1 | expand |
On Thu, 29 Feb 2024 17:35:54 -0600, Adam Ford wrote: > The Beacon board has an LVDS display that cannot get a proper clock rate > from Video_PLL if the DSI is operational due to the way the clock divides > the pixel clocks from video_pll. To make the LVDS work, the LVDS needs > to use an alternative clock. > > Because the clock rated needed for the LDB driving the LVDS display > isn't divisible by the clock rate needed by SAI3, move SAI3 to use > Audio_PLL1, and reconfigure the CODEC to use a 12MHz fixed clock. > > Because these clocks are no longer in sync with each other, the sound > generated as the wrong pitch, so reconfigure the SAI3 to be the master > since the CODEC can internally compensate when fed a fixed clock > reference, even if it is not an even multiple of the desired rate. > > This now leaves AUDIO_PLL2 completely free for the LDB without > compromising the audio sound from the codec. > > Signed-off-by: Adam Ford <aford173@gmail.com> > My bot found new DT warnings on the .dts files added or changed in this series. Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings are fixed by another series. Ultimately, it is up to the platform maintainer whether these warnings are acceptable or not. If you already ran DT checks and didn't see these error(s), then make sure dt-schema is up to date: pip3 install dtschema --upgrade New warnings running 'make CHECK_DTBS=y freescale/imx8mp-beacon-kit.dtb' for 20240229233556.116944-1-aford173@gmail.com: arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dtb: lvds-1: panel-timing:vsync-active:0:0: 3 is not one of [0, 1] from schema $id: http://devicetree.org/schemas/display/panel/panel-lvds.yaml# arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dtb: lvds-1: compatible:0: 'panel-lvds' is not one of ['admatec,9904379', 'auo,b101ew05', 'chunghwa,claa070wp03xg', 'edt,etml0700z9ndha', 'hannstar,hsd101pww2', 'hydis,hv070wx2-1e0', 'tbs,a711-panel'] from schema $id: http://devicetree.org/schemas/display/panel/panel-lvds.yaml# arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dtb: lvds-1: compatible: ['panel-lvds'] is too short from schema $id: http://devicetree.org/schemas/display/panel/panel-lvds.yaml# arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dtb: lvds-1: Unevaluated properties are not allowed ('backlight', 'compatible', 'height-mm', 'panel-timing', 'port', 'power-supply', 'width-mm' were unexpected) from schema $id: http://devicetree.org/schemas/display/panel/panel-lvds.yaml#
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts b/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts index a08057410bde..1f827ef38e36 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts @@ -211,20 +211,20 @@ sound-wm8962 { simple-audio-card,cpu { sound-dai = <&sai3>; + frame-master; + bitclock-master; }; simple-audio-card,codec { sound-dai = <&wm8962>; clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO1>; - frame-master; - bitclock-master; }; }; }; &audio_blk_ctrl { - assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>, <&clk IMX8MP_AUDIO_PLL2>; - assigned-clock-rates = <393216000>, <135475200>; + assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>; + assigned-clock-rates = <393216000>; }; &ecspi2 { @@ -370,8 +370,8 @@ wm8962: audio-codec@1a { pinctrl-0 = <&pinctrl_wm8962>; clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO1>; assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO1>; - assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>; - assigned-clock-rates = <22576000>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <12000000>; DCVDD-supply = <®_audio>; DBVDD-supply = <®_audio>; AVDD-supply = <®_audio>; @@ -499,10 +499,9 @@ &pcie_phy { &sai3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; - assigned-clocks = <&clk IMX8MP_CLK_SAI3>, - <&clk IMX8MP_AUDIO_PLL2> ; - assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>; - assigned-clock-rates = <12288000>, <361267200>; + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; fsl,sai-mclk-direction-output; status = "okay"; };
The Beacon board has an LVDS display that cannot get a proper clock rate from Video_PLL if the DSI is operational due to the way the clock divides the pixel clocks from video_pll. To make the LVDS work, the LVDS needs to use an alternative clock. Because the clock rated needed for the LDB driving the LVDS display isn't divisible by the clock rate needed by SAI3, move SAI3 to use Audio_PLL1, and reconfigure the CODEC to use a 12MHz fixed clock. Because these clocks are no longer in sync with each other, the sound generated as the wrong pitch, so reconfigure the SAI3 to be the master since the CODEC can internally compensate when fed a fixed clock reference, even if it is not an even multiple of the desired rate. This now leaves AUDIO_PLL2 completely free for the LDB without compromising the audio sound from the codec. Signed-off-by: Adam Ford <aford173@gmail.com>