diff mbox series

[v2,4/6] arm64: dts: rockchip: Add device tree support for HDMI RX Controller

Message ID 20240305123648.8847-5-shreeya.patel@collabora.com (mailing list archive)
State New, archived
Headers show
Series Add Synopsys DesignWare HDMI RX Controller | expand

Commit Message

Shreeya Patel March 5, 2024, 12:36 p.m. UTC
Add device tree support for Synopsys DesignWare HDMI RX
Controller.

Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Co-developed-by: Dingxian Wen <shawn.wen@rock-chips.com>
Signed-off-by: Dingxian Wen <shawn.wen@rock-chips.com>
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
---
Changes in v2 :-
  - Fix some of the checkpatch errors and warnings
  - Rename resets, vo1-grf and HPD
  - Move hdmirx_cma node to the rk3588.dtsi file

 .../boot/dts/rockchip/rk3588-pinctrl.dtsi     | 41 ++++++++++++++
 arch/arm64/boot/dts/rockchip/rk3588.dtsi      | 55 +++++++++++++++++++
 2 files changed, 96 insertions(+)

Comments

Heiko Stübner March 5, 2024, 2:11 p.m. UTC | #1
Hi,


Am Dienstag, 5. März 2024, 13:36:46 CET schrieb Shreeya Patel:
> Add device tree support for Synopsys DesignWare HDMI RX
> Controller.
> 
> Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
> Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
> Co-developed-by: Dingxian Wen <shawn.wen@rock-chips.com>
> Signed-off-by: Dingxian Wen <shawn.wen@rock-chips.com>
> Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
> ---
> Changes in v2 :-
>   - Fix some of the checkpatch errors and warnings
>   - Rename resets, vo1-grf and HPD
>   - Move hdmirx_cma node to the rk3588.dtsi file
> 
>  .../boot/dts/rockchip/rk3588-pinctrl.dtsi     | 41 ++++++++++++++
>  arch/arm64/boot/dts/rockchip/rk3588.dtsi      | 55 +++++++++++++++++++
>  2 files changed, 96 insertions(+)

> diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> index 5519c1430cb7..8adb98b99701 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> @@ -7,6 +7,24 @@
>  #include "rk3588-pinctrl.dtsi"
>  
>  / {
> +	reserved-memory {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;

add blank line here

> +		/*
> +		 * The 4k HDMI capture controller works only with 32bit
> +		 * phys addresses and doesn't support IOMMU. HDMI RX CMA
> +		 * must be reserved below 4GB.
> +		 */
> +		hdmirx_cma: hdmirx_cma {

phandles use "_", but node-names "-"

> +			compatible = "shared-dma-pool";
> +			alloc-ranges = <0x0 0x0 0x0 0xffffffff>;
> +			size = <0x0 (160 * 0x100000)>; /* 160MiB */

The comment above that node, could elaborate where the value of 160MB
originates from. I assume it is to hold n-times of 4K frames or whatever,
but it would be helpful for people to be able to read that.


> +			no-map;
> +			status = "disabled";
> +		};
> +	};
> +
>  	pcie30_phy_grf: syscon@fd5b8000 {
>  		compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
>  		reg = <0x0 0xfd5b8000 0x0 0x10000>;
> @@ -85,6 +103,38 @@ i2s10_8ch: i2s@fde00000 {
>  		status = "disabled";
>  	};
>  
> +	hdmi_receiver: hdmi-receiver@fdee0000 {

Maybe rename the label to "hdmirx:" ... that way in a board enabling the
cma region, both nodes would stay close to each other?


> +		compatible = "rockchip,rk3588-hdmirx-ctrler", "snps,dw-hdmi-rx";
> +		reg = <0x0 0xfdee0000 0x0 0x6000>;
> +		power-domains = <&power RK3588_PD_VO1>;
> +		rockchip,grf = <&sys_grf>;
> +		rockchip,vo1-grf = <&vo1_grf>;
> +		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH 0>;
> +		interrupt-names = "cec", "hdmi", "dma";
> +		clocks = <&cru ACLK_HDMIRX>,
> +			 <&cru CLK_HDMIRX_AUD>,
> +			 <&cru CLK_CR_PARA>,
> +			 <&cru PCLK_HDMIRX>,
> +			 <&cru CLK_HDMIRX_REF>,
> +			 <&cru PCLK_S_HDMIRX>,
> +			 <&cru HCLK_VO1>;
> +		clock-names = "aclk",
> +			      "audio",
> +			      "cr_para",
> +			      "pclk",
> +			      "ref",
> +			      "hclk_s_hdmirx",
> +			      "hclk_vo1";

the driver uses of_reserved_mem_device_init(), so doesn't this node need
a "memory-region = <&hdmirx_cma>; or similar?


> +		resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>,
> +			 <&cru SRST_HDMIRX_REF>, <&cru SRST_A_HDMIRX_BIU>;
> +		reset-names = "axi", "apb", "ref", "biu";
> +		pinctrl-0 = <&hdmim1_rx>;
> +		pinctrl-names = "default";
> +		status = "disabled";
> +	};
> +
>  	pcie3x4: pcie@fe150000 {
>  		compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
>  		#address-cells = <3>;
> @@ -339,3 +389,8 @@ pcie30phy: phy@fee80000 {
>  		status = "disabled";
>  	};
>  };
> +
> +&hdmirx_cma {
> +	status = "okay";
> +};

I'd assume a board that enables &hdmi_receiver would also enable hdmirx_cma
and not the soc dtsi for _all_ boards?


Thanks
Heiko
Shreeya Patel March 5, 2024, 7:05 p.m. UTC | #2
On Tuesday, March 05, 2024 19:41 IST, Heiko Stübner <heiko@sntech.de> wrote:

> Hi,
> 

Hi Heiko,

> 
> Am Dienstag, 5. März 2024, 13:36:46 CET schrieb Shreeya Patel:
> > Add device tree support for Synopsys DesignWare HDMI RX
> > Controller.
> > 
> > Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
> > Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
> > Co-developed-by: Dingxian Wen <shawn.wen@rock-chips.com>
> > Signed-off-by: Dingxian Wen <shawn.wen@rock-chips.com>
> > Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
> > ---
> > Changes in v2 :-
> >   - Fix some of the checkpatch errors and warnings
> >   - Rename resets, vo1-grf and HPD
> >   - Move hdmirx_cma node to the rk3588.dtsi file
> > 
> >  .../boot/dts/rockchip/rk3588-pinctrl.dtsi     | 41 ++++++++++++++
> >  arch/arm64/boot/dts/rockchip/rk3588.dtsi      | 55 +++++++++++++++++++
> >  2 files changed, 96 insertions(+)
> 
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> > index 5519c1430cb7..8adb98b99701 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> > +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> > @@ -7,6 +7,24 @@
> >  #include "rk3588-pinctrl.dtsi"
> >  
> >  / {
> > +	reserved-memory {
> > +		#address-cells = <2>;
> > +		#size-cells = <2>;
> > +		ranges;
> 
> add blank line here
> 
> > +		/*
> > +		 * The 4k HDMI capture controller works only with 32bit
> > +		 * phys addresses and doesn't support IOMMU. HDMI RX CMA
> > +		 * must be reserved below 4GB.
> > +		 */
> > +		hdmirx_cma: hdmirx_cma {
> 
> phandles use "_", but node-names "-"
> 
> > +			compatible = "shared-dma-pool";
> > +			alloc-ranges = <0x0 0x0 0x0 0xffffffff>;
> > +			size = <0x0 (160 * 0x100000)>; /* 160MiB */
> 
> The comment above that node, could elaborate where the value of 160MB
> originates from. I assume it is to hold n-times of 4K frames or whatever,
> but it would be helpful for people to be able to read that.
> 

right, we did the following calculation to come up with this value :-
3840 * 2160 * 4 (bytes/pix) * 2 (frames/buffer) / 1000 / 1000 = 66M
and then we do the 2x times of this value to be on the safer side
and support all practical use-cases.

I'll add some more details to the comment in v3.

> 
> > +			no-map;
> > +			status = "disabled";
> > +		};
> > +	};
> > +
> >  	pcie30_phy_grf: syscon@fd5b8000 {
> >  		compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
> >  		reg = <0x0 0xfd5b8000 0x0 0x10000>;
> > @@ -85,6 +103,38 @@ i2s10_8ch: i2s@fde00000 {
> >  		status = "disabled";
> >  	};
> >  
> > +	hdmi_receiver: hdmi-receiver@fdee0000 {
> 
> Maybe rename the label to "hdmirx:" ... that way in a board enabling the
> cma region, both nodes would stay close to each other?
> 

Umm we already have receiver in the name so I am not sure if adding rx will be
a good idea. I was trying to keep it consistent with the names used in other device tree files.
In case you still feel otherwise then do let me know, I'll make the change.

> 
> > +		compatible = "rockchip,rk3588-hdmirx-ctrler", "snps,dw-hdmi-rx";
> > +		reg = <0x0 0xfdee0000 0x0 0x6000>;
> > +		power-domains = <&power RK3588_PD_VO1>;
> > +		rockchip,grf = <&sys_grf>;
> > +		rockchip,vo1-grf = <&vo1_grf>;
> > +		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0>,
> > +			     <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH 0>,
> > +			     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH 0>;
> > +		interrupt-names = "cec", "hdmi", "dma";
> > +		clocks = <&cru ACLK_HDMIRX>,
> > +			 <&cru CLK_HDMIRX_AUD>,
> > +			 <&cru CLK_CR_PARA>,
> > +			 <&cru PCLK_HDMIRX>,
> > +			 <&cru CLK_HDMIRX_REF>,
> > +			 <&cru PCLK_S_HDMIRX>,
> > +			 <&cru HCLK_VO1>;
> > +		clock-names = "aclk",
> > +			      "audio",
> > +			      "cr_para",
> > +			      "pclk",
> > +			      "ref",
> > +			      "hclk_s_hdmirx",
> > +			      "hclk_vo1";
> 
> the driver uses of_reserved_mem_device_init(), so doesn't this node need
> a "memory-region = <&hdmirx_cma>; or similar?
> 

yes, we should have the memory-region property here. My bad, I'll correct this in v3.

> 
> > +		resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>,
> > +			 <&cru SRST_HDMIRX_REF>, <&cru SRST_A_HDMIRX_BIU>;
> > +		reset-names = "axi", "apb", "ref", "biu";
> > +		pinctrl-0 = <&hdmim1_rx>;
> > +		pinctrl-names = "default";
> > +		status = "disabled";
> > +	};
> > +
> >  	pcie3x4: pcie@fe150000 {
> >  		compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
> >  		#address-cells = <3>;
> > @@ -339,3 +389,8 @@ pcie30phy: phy@fee80000 {
> >  		status = "disabled";
> >  	};
> >  };
> > +
> > +&hdmirx_cma {
> > +	status = "okay";
> > +};
> 
> I'd assume a board that enables &hdmi_receiver would also enable hdmirx_cma
> and not the soc dtsi for _all_ boards?
> 

Actually this node should be in the rock-5b.dts file instead of here.
v1 had it correct but I made a mistake in v2 :(
Thanks for pointing this out, I'll fix this and send a v3 soon.


Thanks,
Shreeya Patel

> 
> Thanks
> Heiko
> 
> 
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Heiko Stübner March 5, 2024, 8:20 p.m. UTC | #3
Hi again :-)

Am Dienstag, 5. März 2024, 20:05:02 CET schrieb Shreeya Patel:
> On Tuesday, March 05, 2024 19:41 IST, Heiko Stübner <heiko@sntech.de> wrote:
> > Am Dienstag, 5. März 2024, 13:36:46 CET schrieb Shreeya Patel:
> > > Add device tree support for Synopsys DesignWare HDMI RX
> > > Controller.
> > > 
> > > Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
> > > Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
> > > Co-developed-by: Dingxian Wen <shawn.wen@rock-chips.com>
> > > Signed-off-by: Dingxian Wen <shawn.wen@rock-chips.com>
> > > Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
> > > ---
> > > Changes in v2 :-
> > >   - Fix some of the checkpatch errors and warnings
> > >   - Rename resets, vo1-grf and HPD
> > >   - Move hdmirx_cma node to the rk3588.dtsi file
> > > 
> > >  .../boot/dts/rockchip/rk3588-pinctrl.dtsi     | 41 ++++++++++++++
> > >  arch/arm64/boot/dts/rockchip/rk3588.dtsi      | 55 +++++++++++++++++++
> > >  2 files changed, 96 insertions(+)
> > 
> > > diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> > > index 5519c1430cb7..8adb98b99701 100644
> > > --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> > > +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> > > @@ -7,6 +7,24 @@
> > >  #include "rk3588-pinctrl.dtsi"
> > >  
> > >  / {
> > > +	reserved-memory {
> > > +		#address-cells = <2>;
> > > +		#size-cells = <2>;
> > > +		ranges;
> > 
> > add blank line here
> > 
> > > +		/*
> > > +		 * The 4k HDMI capture controller works only with 32bit
> > > +		 * phys addresses and doesn't support IOMMU. HDMI RX CMA
> > > +		 * must be reserved below 4GB.
> > > +		 */
> > > +		hdmirx_cma: hdmirx_cma {
> > 
> > phandles use "_", but node-names "-"
> > 
> > > +			compatible = "shared-dma-pool";
> > > +			alloc-ranges = <0x0 0x0 0x0 0xffffffff>;
> > > +			size = <0x0 (160 * 0x100000)>; /* 160MiB */
> > 
> > The comment above that node, could elaborate where the value of 160MB
> > originates from. I assume it is to hold n-times of 4K frames or whatever,
> > but it would be helpful for people to be able to read that.
> > 
> 
> right, we did the following calculation to come up with this value :-
> 3840 * 2160 * 4 (bytes/pix) * 2 (frames/buffer) / 1000 / 1000 = 66M
> and then we do the 2x times of this value to be on the safer side
> and support all practical use-cases.
> 
> I'll add some more details to the comment in v3.

thanks, that will be helpful for me and everybody reading the dts later on

> 
> > 
> > > +			no-map;
> > > +			status = "disabled";
> > > +		};
> > > +	};
> > > +
> > >  	pcie30_phy_grf: syscon@fd5b8000 {
> > >  		compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
> > >  		reg = <0x0 0xfd5b8000 0x0 0x10000>;
> > > @@ -85,6 +103,38 @@ i2s10_8ch: i2s@fde00000 {
> > >  		status = "disabled";
> > >  	};
> > >  
> > > +	hdmi_receiver: hdmi-receiver@fdee0000 {
> > 
> > Maybe rename the label to "hdmirx:" ... that way in a board enabling the
> > cma region, both nodes would stay close to each other?
> > 
> 
> Umm we already have receiver in the name so I am not sure if adding rx will be
> a good idea. I was trying to keep it consistent with the names used in other device tree files.
> In case you still feel otherwise then do let me know, I'll make the change.

I'm somewhat partial to the actual name, I was more getting at similar
names to keep things together.

General sorting rules are that &foo phandles are sorted alphabetically
in board devicetrees.

So having

&hdmirx {
	status = "okay";
};

&hdmirx_cma {
	status = "okay";
};

in the board dt, makes them stay together automatically ;-)

So if it's hdmirx + hdmirx_cma or hdmi_receiver + hdmi_receiver_cma
doesn't matter that much, just that they share a common basename.


I really want to stay away from allowing special rules for things as much
as possible, because that becomes a neverending story, so it's
alphabetical sorting.

But nothing prevents us from naming phandles in an intelligent way ;-) .


Thanks
Heiko

> > > +		compatible = "rockchip,rk3588-hdmirx-ctrler", "snps,dw-hdmi-rx";
> > > +		reg = <0x0 0xfdee0000 0x0 0x6000>;
> > > +		power-domains = <&power RK3588_PD_VO1>;
> > > +		rockchip,grf = <&sys_grf>;
> > > +		rockchip,vo1-grf = <&vo1_grf>;
> > > +		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0>,
> > > +			     <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH 0>,
> > > +			     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH 0>;
> > > +		interrupt-names = "cec", "hdmi", "dma";
> > > +		clocks = <&cru ACLK_HDMIRX>,
> > > +			 <&cru CLK_HDMIRX_AUD>,
> > > +			 <&cru CLK_CR_PARA>,
> > > +			 <&cru PCLK_HDMIRX>,
> > > +			 <&cru CLK_HDMIRX_REF>,
> > > +			 <&cru PCLK_S_HDMIRX>,
> > > +			 <&cru HCLK_VO1>;
> > > +		clock-names = "aclk",
> > > +			      "audio",
> > > +			      "cr_para",
> > > +			      "pclk",
> > > +			      "ref",
> > > +			      "hclk_s_hdmirx",
> > > +			      "hclk_vo1";
> > 
> > the driver uses of_reserved_mem_device_init(), so doesn't this node need
> > a "memory-region = <&hdmirx_cma>; or similar?
> > 
> 
> yes, we should have the memory-region property here. My bad, I'll correct this in v3.
> 
> > 
> > > +		resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>,
> > > +			 <&cru SRST_HDMIRX_REF>, <&cru SRST_A_HDMIRX_BIU>;
> > > +		reset-names = "axi", "apb", "ref", "biu";
> > > +		pinctrl-0 = <&hdmim1_rx>;
> > > +		pinctrl-names = "default";
> > > +		status = "disabled";
> > > +	};
> > > +
> > >  	pcie3x4: pcie@fe150000 {
> > >  		compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
> > >  		#address-cells = <3>;
> > > @@ -339,3 +389,8 @@ pcie30phy: phy@fee80000 {
> > >  		status = "disabled";
> > >  	};
> > >  };
> > > +
> > > +&hdmirx_cma {
> > > +	status = "okay";
> > > +};
> > 
> > I'd assume a board that enables &hdmi_receiver would also enable hdmirx_cma
> > and not the soc dtsi for _all_ boards?
> > 
> 
> Actually this node should be in the rock-5b.dts file instead of here.
> v1 had it correct but I made a mistake in v2 :(
> Thanks for pointing this out, I'll fix this and send a v3 soon.
Shreeya Patel March 6, 2024, 7:28 p.m. UTC | #4
On Wednesday, March 06, 2024 01:50 IST, Heiko Stübner <heiko@sntech.de> wrote:

> Hi again :-)
> 
> Am Dienstag, 5. März 2024, 20:05:02 CET schrieb Shreeya Patel:
> > On Tuesday, March 05, 2024 19:41 IST, Heiko Stübner <heiko@sntech.de> wrote:
> > > Am Dienstag, 5. März 2024, 13:36:46 CET schrieb Shreeya Patel:
> > > > Add device tree support for Synopsys DesignWare HDMI RX
> > > > Controller.
> > > > 
> > > > Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
> > > > Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
> > > > Co-developed-by: Dingxian Wen <shawn.wen@rock-chips.com>
> > > > Signed-off-by: Dingxian Wen <shawn.wen@rock-chips.com>
> > > > Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
> > > > ---
> > > > Changes in v2 :-
> > > >   - Fix some of the checkpatch errors and warnings
> > > >   - Rename resets, vo1-grf and HPD
> > > >   - Move hdmirx_cma node to the rk3588.dtsi file
> > > > 
> > > >  .../boot/dts/rockchip/rk3588-pinctrl.dtsi     | 41 ++++++++++++++
> > > >  arch/arm64/boot/dts/rockchip/rk3588.dtsi      | 55 +++++++++++++++++++
> > > >  2 files changed, 96 insertions(+)
> > > 
> > > > diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> > > > index 5519c1430cb7..8adb98b99701 100644
> > > > --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> > > > +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> > > > @@ -7,6 +7,24 @@
> > > >  #include "rk3588-pinctrl.dtsi"
> > > >  
> > > >  / {
> > > > +	reserved-memory {
> > > > +		#address-cells = <2>;
> > > > +		#size-cells = <2>;
> > > > +		ranges;
> > > 
> > > add blank line here
> > > 
> > > > +		/*
> > > > +		 * The 4k HDMI capture controller works only with 32bit
> > > > +		 * phys addresses and doesn't support IOMMU. HDMI RX CMA
> > > > +		 * must be reserved below 4GB.
> > > > +		 */
> > > > +		hdmirx_cma: hdmirx_cma {
> > > 
> > > phandles use "_", but node-names "-"
> > > 
> > > > +			compatible = "shared-dma-pool";
> > > > +			alloc-ranges = <0x0 0x0 0x0 0xffffffff>;
> > > > +			size = <0x0 (160 * 0x100000)>; /* 160MiB */
> > > 
> > > The comment above that node, could elaborate where the value of 160MB
> > > originates from. I assume it is to hold n-times of 4K frames or whatever,
> > > but it would be helpful for people to be able to read that.
> > > 
> > 
> > right, we did the following calculation to come up with this value :-
> > 3840 * 2160 * 4 (bytes/pix) * 2 (frames/buffer) / 1000 / 1000 = 66M
> > and then we do the 2x times of this value to be on the safer side
> > and support all practical use-cases.
> > 
> > I'll add some more details to the comment in v3.
> 
> thanks, that will be helpful for me and everybody reading the dts later on
> 
> > 
> > > 
> > > > +			no-map;
> > > > +			status = "disabled";
> > > > +		};
> > > > +	};
> > > > +
> > > >  	pcie30_phy_grf: syscon@fd5b8000 {
> > > >  		compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
> > > >  		reg = <0x0 0xfd5b8000 0x0 0x10000>;
> > > > @@ -85,6 +103,38 @@ i2s10_8ch: i2s@fde00000 {
> > > >  		status = "disabled";
> > > >  	};
> > > >  
> > > > +	hdmi_receiver: hdmi-receiver@fdee0000 {
> > > 
> > > Maybe rename the label to "hdmirx:" ... that way in a board enabling the
> > > cma region, both nodes would stay close to each other?
> > > 
> > 
> > Umm we already have receiver in the name so I am not sure if adding rx will be
> > a good idea. I was trying to keep it consistent with the names used in other device tree files.
> > In case you still feel otherwise then do let me know, I'll make the change.
> 
> I'm somewhat partial to the actual name, I was more getting at similar
> names to keep things together.
> 
> General sorting rules are that &foo phandles are sorted alphabetically
> in board devicetrees.
> 
> So having
> 
> &hdmirx {
> 	status = "okay";
> };
> 
> &hdmirx_cma {
> 	status = "okay";
> };
> 
> in the board dt, makes them stay together automatically ;-)
> 
> So if it's hdmirx + hdmirx_cma or hdmi_receiver + hdmi_receiver_cma
> doesn't matter that much, just that they share a common basename.
> 
> 
> I really want to stay away from allowing special rules for things as much
> as possible, because that becomes a neverending story, so it's
> alphabetical sorting.
> 
> But nothing prevents us from naming phandles in an intelligent way ;-) .
> 

Makes sense to me, I'll use hdmi_receiver + hdmi_receiver_cma combination
to keep it consistent.

Thanks,
Shreeya Patel

> 
> Thanks
> Heiko
>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-pinctrl.dtsi
index 244c66faa161..4fbe194d96b1 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-pinctrl.dtsi
@@ -169,6 +169,47 @@  hdmim0_tx1_sda: hdmim0-tx1-sda {
 				/* hdmim0_tx1_sda */
 				<2 RK_PB4 4 &pcfg_pull_none>;
 		};
+
+		/omit-if-no-ref/
+		hdmim1_rx: hdmim1-rx {
+			rockchip,pins =
+				/* hdmim1_rx_cec */
+				<3 RK_PD1 5 &pcfg_pull_none>,
+				/* hdmim1_rx_scl */
+				<3 RK_PD2 5 &pcfg_pull_none_smt>,
+				/* hdmim1_rx_sda */
+				<3 RK_PD3 5 &pcfg_pull_none_smt>,
+				/* hdmim1_rx_hpdin */
+				<3 RK_PD4 5 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		hdmim1_rx_cec: hdmim1-rx-cec {
+			rockchip,pins =
+				/* hdmim1_rx_cec */
+				<3 RK_PD1 5 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		hdmim1_rx_hpdin: hdmim1-rx-hpdin {
+			rockchip,pins =
+				/* hdmim1_rx_hpdin */
+				<3 RK_PD4 5 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		hdmim1_rx_scl: hdmim1-rx-scl {
+			rockchip,pins =
+				/* hdmim1_rx_scl */
+				<3 RK_PD2 5 &pcfg_pull_none>;
+		};
+
+		/omit-if-no-ref/
+		hdmim1_rx_sda: hdmim1-rx-sda {
+			rockchip,pins =
+				/* hdmim1_rx_sda */
+				<3 RK_PD3 5 &pcfg_pull_none>;
+		};
 	};
 
 	i2c0 {
diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
index 5519c1430cb7..8adb98b99701 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
@@ -7,6 +7,24 @@ 
 #include "rk3588-pinctrl.dtsi"
 
 / {
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		/*
+		 * The 4k HDMI capture controller works only with 32bit
+		 * phys addresses and doesn't support IOMMU. HDMI RX CMA
+		 * must be reserved below 4GB.
+		 */
+		hdmirx_cma: hdmirx_cma {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0x0 0x0 0x0 0xffffffff>;
+			size = <0x0 (160 * 0x100000)>; /* 160MiB */
+			no-map;
+			status = "disabled";
+		};
+	};
+
 	pcie30_phy_grf: syscon@fd5b8000 {
 		compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
 		reg = <0x0 0xfd5b8000 0x0 0x10000>;
@@ -85,6 +103,38 @@  i2s10_8ch: i2s@fde00000 {
 		status = "disabled";
 	};
 
+	hdmi_receiver: hdmi-receiver@fdee0000 {
+		compatible = "rockchip,rk3588-hdmirx-ctrler", "snps,dw-hdmi-rx";
+		reg = <0x0 0xfdee0000 0x0 0x6000>;
+		power-domains = <&power RK3588_PD_VO1>;
+		rockchip,grf = <&sys_grf>;
+		rockchip,vo1-grf = <&vo1_grf>;
+		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH 0>;
+		interrupt-names = "cec", "hdmi", "dma";
+		clocks = <&cru ACLK_HDMIRX>,
+			 <&cru CLK_HDMIRX_AUD>,
+			 <&cru CLK_CR_PARA>,
+			 <&cru PCLK_HDMIRX>,
+			 <&cru CLK_HDMIRX_REF>,
+			 <&cru PCLK_S_HDMIRX>,
+			 <&cru HCLK_VO1>;
+		clock-names = "aclk",
+			      "audio",
+			      "cr_para",
+			      "pclk",
+			      "ref",
+			      "hclk_s_hdmirx",
+			      "hclk_vo1";
+		resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>,
+			 <&cru SRST_HDMIRX_REF>, <&cru SRST_A_HDMIRX_BIU>;
+		reset-names = "axi", "apb", "ref", "biu";
+		pinctrl-0 = <&hdmim1_rx>;
+		pinctrl-names = "default";
+		status = "disabled";
+	};
+
 	pcie3x4: pcie@fe150000 {
 		compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
 		#address-cells = <3>;
@@ -339,3 +389,8 @@  pcie30phy: phy@fee80000 {
 		status = "disabled";
 	};
 };
+
+&hdmirx_cma {
+	status = "okay";
+};
+