| Message ID | 20240311175926.1625180-3-tanmay.shah@amd.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | add zynqmp TCM bindings | expand |
On 11/03/2024 18:59, Tanmay Shah wrote: > From: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > > Introduce bindings for TCM memory address space on AMD-xilinx Zynq > UltraScale+ platform. It will help in defining TCM in device-tree > and make it's access platform agnostic and data-driven. > > Tightly-coupled memories(TCMs) are low-latency memory that provides > predictable instruction execution and predictable data load/store > timing. Each Cortex-R5F processor contains two 64-bit wide 64 KB memory > banks on the ATCM and BTCM ports, for a total of 128 KB of memory. > > The TCM resources(reg, reg-names and power-domain) are documented for > each TCM in the R5 node. The reg and reg-names are made as required > properties as we don't want to hardcode TCM addresses for future > platforms and for zu+ legacy implementation will ensure that the > old dts w/o reg/reg-names works and stable ABI is maintained. > > It also extends the examples for TCM split and lockstep modes. > > Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > Signed-off-by: Tanmay Shah <tanmay.shah@amd.com> > --- > > Changes in v13: > - Have power-domains property for lockstep case instead of > keeping it flexible. > - Add "items:" list in power-domains property Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On 3/12/24 7:13 AM, Krzysztof Kozlowski wrote: > On 11/03/2024 18:59, Tanmay Shah wrote: >> From: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> >> >> Introduce bindings for TCM memory address space on AMD-xilinx Zynq >> UltraScale+ platform. It will help in defining TCM in device-tree >> and make it's access platform agnostic and data-driven. >> >> Tightly-coupled memories(TCMs) are low-latency memory that provides >> predictable instruction execution and predictable data load/store >> timing. Each Cortex-R5F processor contains two 64-bit wide 64 KB memory >> banks on the ATCM and BTCM ports, for a total of 128 KB of memory. >> >> The TCM resources(reg, reg-names and power-domain) are documented for >> each TCM in the R5 node. The reg and reg-names are made as required >> properties as we don't want to hardcode TCM addresses for future >> platforms and for zu+ legacy implementation will ensure that the >> old dts w/o reg/reg-names works and stable ABI is maintained. >> >> It also extends the examples for TCM split and lockstep modes. >> >> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> >> Signed-off-by: Tanmay Shah <tanmay.shah@amd.com> >> --- >> >> Changes in v13: >> - Have power-domains property for lockstep case instead of >> keeping it flexible. >> - Add "items:" list in power-domains property > > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Hi Krzysztof, Thanks for RB. I provided explanation of flexible power-domains in previous patchset. I am happy to send new revision removing minItems if you dis-agree. Thanks. > > Best regards, > Krzysztof >
On 12/03/2024 18:42, Tanmay Shah wrote: > > > On 3/12/24 7:13 AM, Krzysztof Kozlowski wrote: >> On 11/03/2024 18:59, Tanmay Shah wrote: >>> From: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> >>> >>> Introduce bindings for TCM memory address space on AMD-xilinx Zynq >>> UltraScale+ platform. It will help in defining TCM in device-tree >>> and make it's access platform agnostic and data-driven. >>> >>> Tightly-coupled memories(TCMs) are low-latency memory that provides >>> predictable instruction execution and predictable data load/store >>> timing. Each Cortex-R5F processor contains two 64-bit wide 64 KB memory >>> banks on the ATCM and BTCM ports, for a total of 128 KB of memory. >>> >>> The TCM resources(reg, reg-names and power-domain) are documented for >>> each TCM in the R5 node. The reg and reg-names are made as required >>> properties as we don't want to hardcode TCM addresses for future >>> platforms and for zu+ legacy implementation will ensure that the >>> old dts w/o reg/reg-names works and stable ABI is maintained. >>> >>> It also extends the examples for TCM split and lockstep modes. >>> >>> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> >>> Signed-off-by: Tanmay Shah <tanmay.shah@amd.com> >>> --- >>> >>> Changes in v13: >>> - Have power-domains property for lockstep case instead of >>> keeping it flexible. >>> - Add "items:" list in power-domains property >> >> >> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > > Hi Krzysztof, > > Thanks for RB. I provided explanation of flexible power-domains in > previous patchset. I am happy to send new revision removing > minItems if you dis-agree. Thanks for the explanation, it sounds fine, thus patch LGTM. Best regards, Krzysztof
On 12/03/2024 13:13, Krzysztof Kozlowski wrote: > On 11/03/2024 18:59, Tanmay Shah wrote: >> From: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> >> >> Introduce bindings for TCM memory address space on AMD-xilinx Zynq >> UltraScale+ platform. It will help in defining TCM in device-tree >> and make it's access platform agnostic and data-driven. >> >> Tightly-coupled memories(TCMs) are low-latency memory that provides >> predictable instruction execution and predictable data load/store >> timing. Each Cortex-R5F processor contains two 64-bit wide 64 KB memory >> banks on the ATCM and BTCM ports, for a total of 128 KB of memory. >> >> The TCM resources(reg, reg-names and power-domain) are documented for >> each TCM in the R5 node. The reg and reg-names are made as required >> properties as we don't want to hardcode TCM addresses for future >> platforms and for zu+ legacy implementation will ensure that the >> old dts w/o reg/reg-names works and stable ABI is maintained. >> >> It also extends the examples for TCM split and lockstep modes. >> >> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> >> Signed-off-by: Tanmay Shah <tanmay.shah@amd.com> >> --- >> >> Changes in v13: >> - Have power-domains property for lockstep case instead of >> keeping it flexible. >> - Add "items:" list in power-domains property > > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> And unreviewed. It turns out you now mix devices and bring incompatible programming models under one compatible. And this leads to problems in your further patches. NAK. Best regards, Krzysztof
On 11/03/2024 18:59, Tanmay Shah wrote: > From: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > > Introduce bindings for TCM memory address space on AMD-xilinx Zynq > UltraScale+ platform. It will help in defining TCM in device-tree > and make it's access platform agnostic and data-driven. > > Tightly-coupled memories(TCMs) are low-latency memory that provides > predictable instruction execution and predictable data load/store > timing. Each Cortex-R5F processor contains two 64-bit wide 64 KB memory > banks on the ATCM and BTCM ports, for a total of 128 KB of memory. > > The TCM resources(reg, reg-names and power-domain) are documented for > each TCM in the R5 node. The reg and reg-names are made as required > properties as we don't want to hardcode TCM addresses for future > platforms and for zu+ legacy implementation will ensure that the > old dts w/o reg/reg-names works and stable ABI is maintained. > > It also extends the examples for TCM split and lockstep modes. > > Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > Signed-off-by: Tanmay Shah <tanmay.shah@amd.com> > --- I responded under my reviewed-tag, but to be clear, also here: This patch has is not ready. Please do not merge. Best regards, Krzysztof
On 3/19/24 12:29 AM, Krzysztof Kozlowski wrote: > On 11/03/2024 18:59, Tanmay Shah wrote: >> From: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> >> >> Introduce bindings for TCM memory address space on AMD-xilinx Zynq >> UltraScale+ platform. It will help in defining TCM in device-tree >> and make it's access platform agnostic and data-driven. >> >> Tightly-coupled memories(TCMs) are low-latency memory that provides >> predictable instruction execution and predictable data load/store >> timing. Each Cortex-R5F processor contains two 64-bit wide 64 KB memory >> banks on the ATCM and BTCM ports, for a total of 128 KB of memory. >> >> The TCM resources(reg, reg-names and power-domain) are documented for >> each TCM in the R5 node. The reg and reg-names are made as required >> properties as we don't want to hardcode TCM addresses for future >> platforms and for zu+ legacy implementation will ensure that the >> old dts w/o reg/reg-names works and stable ABI is maintained. >> >> It also extends the examples for TCM split and lockstep modes. >> >> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> >> Signed-off-by: Tanmay Shah <tanmay.shah@amd.com> >> --- > > I responded under my reviewed-tag, but to be clear, also here: > > This patch has is not ready. Please do not merge. > Glad we could catch this before merging this. I will wait for your reply on other thread for refactoring. > Best regards, > Krzysztof >
diff --git a/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml b/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml index 78aac69f1060..629084a84ce6 100644 --- a/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml +++ b/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml @@ -20,9 +20,21 @@ properties: compatible: const: xlnx,zynqmp-r5fss + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: + description: | + Standard ranges definition providing address translations for + local R5F TCM address spaces to bus addresses. + xlnx,cluster-mode: $ref: /schemas/types.yaml#/definitions/uint32 enum: [0, 1, 2] + default: 1 description: | The RPU MPCore can operate in split mode (Dual-processor performance), Safety lock-step mode(Both RPU cores execute the same code in lock-step, @@ -37,7 +49,7 @@ properties: 2: single cpu mode patternProperties: - "^r5f-[a-f0-9]+$": + "^r5f@[0-9a-f]+$": type: object description: | The RPU is located in the Low Power Domain of the Processor Subsystem. @@ -54,8 +66,17 @@ patternProperties: compatible: const: xlnx,zynqmp-r5f + reg: + minItems: 1 + maxItems: 4 + + reg-names: + minItems: 1 + maxItems: 4 + power-domains: - maxItems: 1 + minItems: 2 + maxItems: 5 mboxes: minItems: 1 @@ -101,35 +122,175 @@ patternProperties: required: - compatible + - reg + - reg-names - power-domains - unevaluatedProperties: false - required: - compatible + - "#address-cells" + - "#size-cells" + - ranges + +allOf: + - if: + properties: + xlnx,cluster-mode: + enum: + - 1 + then: + patternProperties: + "^r5f@[0-9a-f]+$": + type: object + + properties: + reg: + minItems: 1 + items: + - description: ATCM internal memory + - description: BTCM internal memory + - description: extra ATCM memory in lockstep mode + - description: extra BTCM memory in lockstep mode + + reg-names: + minItems: 1 + items: + - const: atcm0 + - const: btcm0 + - const: atcm1 + - const: btcm1 + + power-domains: + minItems: 2 + items: + - description: RPU core power domain + - description: ATCM power domain + - description: BTCM power domain + - description: second ATCM power domain + - description: second BTCM power domain + + else: + patternProperties: + "^r5f@[0-9a-f]+$": + type: object + + properties: + reg: + minItems: 1 + items: + - description: ATCM internal memory + - description: BTCM internal memory + + reg-names: + minItems: 1 + items: + - const: atcm0 + - const: btcm0 + + power-domains: + minItems: 2 + items: + - description: RPU core power domain + - description: ATCM power domain + - description: BTCM power domain additionalProperties: false examples: - | - remoteproc { - compatible = "xlnx,zynqmp-r5fss"; - xlnx,cluster-mode = <1>; - - r5f-0 { - compatible = "xlnx,zynqmp-r5f"; - power-domains = <&zynqmp_firmware 0x7>; - memory-region = <&rproc_0_fw_image>, <&rpu0vdev0buffer>, <&rpu0vdev0vring0>, <&rpu0vdev0vring1>; - mboxes = <&ipi_mailbox_rpu0 0>, <&ipi_mailbox_rpu0 1>; - mbox-names = "tx", "rx"; + #include <dt-bindings/power/xlnx-zynqmp-power.h> + + // Split mode configuration + soc { + #address-cells = <2>; + #size-cells = <2>; + + remoteproc@ffe00000 { + compatible = "xlnx,zynqmp-r5fss"; + xlnx,cluster-mode = <0>; + + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>, + <0x0 0x20000 0x0 0xffe20000 0x0 0x10000>, + <0x1 0x0 0x0 0xffe90000 0x0 0x10000>, + <0x1 0x20000 0x0 0xffeb0000 0x0 0x10000>; + + r5f@0 { + compatible = "xlnx,zynqmp-r5f"; + reg = <0x0 0x0 0x0 0x10000>, <0x0 0x20000 0x0 0x10000>; + reg-names = "atcm0", "btcm0"; + power-domains = <&zynqmp_firmware PD_RPU_0>, + <&zynqmp_firmware PD_R5_0_ATCM>, + <&zynqmp_firmware PD_R5_0_BTCM>; + memory-region = <&rproc_0_fw_image>, <&rpu0vdev0buffer>, + <&rpu0vdev0vring0>, <&rpu0vdev0vring1>; + mboxes = <&ipi_mailbox_rpu0 0>, <&ipi_mailbox_rpu0 1>; + mbox-names = "tx", "rx"; + }; + + r5f@1 { + compatible = "xlnx,zynqmp-r5f"; + reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>; + reg-names = "atcm0", "btcm0"; + power-domains = <&zynqmp_firmware PD_RPU_1>, + <&zynqmp_firmware PD_R5_1_ATCM>, + <&zynqmp_firmware PD_R5_1_BTCM>; + memory-region = <&rproc_1_fw_image>, <&rpu1vdev0buffer>, + <&rpu1vdev0vring0>, <&rpu1vdev0vring1>; + mboxes = <&ipi_mailbox_rpu1 0>, <&ipi_mailbox_rpu1 1>; + mbox-names = "tx", "rx"; + }; }; + }; + + - | + //Lockstep configuration + soc { + #address-cells = <2>; + #size-cells = <2>; + + remoteproc@ffe00000 { + compatible = "xlnx,zynqmp-r5fss"; + xlnx,cluster-mode = <1>; + + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>, + <0x0 0x20000 0x0 0xffe20000 0x0 0x10000>, + <0x0 0x10000 0x0 0xffe10000 0x0 0x10000>, + <0x0 0x30000 0x0 0xffe30000 0x0 0x10000>; + + r5f@0 { + compatible = "xlnx,zynqmp-r5f"; + reg = <0x0 0x0 0x0 0x10000>, + <0x0 0x20000 0x0 0x10000>, + <0x0 0x10000 0x0 0x10000>, + <0x0 0x30000 0x0 0x10000>; + reg-names = "atcm0", "btcm0", "atcm1", "btcm1"; + power-domains = <&zynqmp_firmware PD_RPU_0>, + <&zynqmp_firmware PD_R5_0_ATCM>, + <&zynqmp_firmware PD_R5_0_BTCM>, + <&zynqmp_firmware PD_R5_1_ATCM>, + <&zynqmp_firmware PD_R5_1_BTCM>; + memory-region = <&rproc_0_fw_image>, <&rpu0vdev0buffer>, + <&rpu0vdev0vring0>, <&rpu0vdev0vring1>; + mboxes = <&ipi_mailbox_rpu0 0>, <&ipi_mailbox_rpu0 1>; + mbox-names = "tx", "rx"; + }; - r5f-1 { - compatible = "xlnx,zynqmp-r5f"; - power-domains = <&zynqmp_firmware 0x8>; - memory-region = <&rproc_1_fw_image>, <&rpu1vdev0buffer>, <&rpu1vdev0vring0>, <&rpu1vdev0vring1>; - mboxes = <&ipi_mailbox_rpu1 0>, <&ipi_mailbox_rpu1 1>; - mbox-names = "tx", "rx"; + r5f@1 { + compatible = "xlnx,zynqmp-r5f"; + reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>; + reg-names = "atcm0", "btcm0"; + power-domains = <&zynqmp_firmware PD_RPU_1>, + <&zynqmp_firmware PD_R5_1_ATCM>, + <&zynqmp_firmware PD_R5_1_BTCM>; + memory-region = <&rproc_1_fw_image>, <&rpu1vdev0buffer>, + <&rpu1vdev0vring0>, <&rpu1vdev0vring1>; + mboxes = <&ipi_mailbox_rpu1 0>, <&ipi_mailbox_rpu1 1>; + mbox-names = "tx", "rx"; + }; }; }; ...