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Thu, 14 Mar 2024 02:42:19 -0700 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 14 Mar 2024 17:41:44 +0800 Received: from mszsdhlt06.gcn.mediatek.inc (10.16.6.206) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 14 Mar 2024 17:41:44 +0800 From: Shuijing Li To: , , , , , , CC: , , , , , Shuijing Li Subject: [PATCH] mediatek: dsi: Add dsi per-frame lp code for mt8188 Date: Thu, 14 Mar 2024 17:41:55 +0800 Message-ID: <20240314094238.3315-1-shuijing.li@mediatek.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--8.397200-8.000000 X-TMASE-MatchedRID: S534RugKI8kwKP61E4rxu1VN8laWo90M5TpDO1WKs2mYQOVjVNfbbkeC RUBS/4NPo5qw/iFKtvYWHIQM6TbbE5Rho78T5P9D4pdq9sdj8LXlNvCpVWkX4+8+PNqCaHTUQ5K Zv/QHc1GfUW6RBS3uLULpsu+J7FFsoT61G3YSs7mQ+gWwzffozrn7V+KB+3cumyiLZetSf8lRN1 j+Z19Ne0kpbiYOUmwxwrbXMGDYqV/Ix3Icp6zuW/Y8Q+obMpZDGRigQm9wRcMFWmWkIG9aWWkGC AUz36Zl X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--8.397200-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 967D6EFB6CEC7F978B2E6FDC292789DF1CF8A4A7AC9EBA50C3B0564A1B37B9FE2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240314_024224_068324_2F046B7F X-CRM114-Status: GOOD ( 12.63 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Adding the per-frame lp function of mt8188, which can keep HFP in HS and reduce the time required for each line to enter and exit low power. Per Frame LP: |<----------One Active Frame-------->| --______________________________________----___________________ ^HSA+HBP^^RGB^^HFP^^HSA+HBP^^RGB^^HFP^ ^HSA+HBP^^RGB^^HFP^ Per Line LP: |<---------------One Active Frame----------->| --______________--______________--______________----______________ ^HSA+HBP^^RGB^ ^HSA+HBP^^RGB^ ^HSA+HBP^^RGB^ ^HSA+HBP^^RGB^ Signed-off-by: Shuijing Li --- drivers/gpu/drm/mediatek/mtk_dsi.c | 100 +++++++++++++++++++++++++++++ 1 file changed, 100 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index a2fdfc8ddb15..e6f4807c8711 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -83,6 +83,7 @@ #define DSI_HSA_WC 0x50 #define DSI_HBP_WC 0x54 #define DSI_HFP_WC 0x58 +#define DSI_BLLP_WC 0x5C #define DSI_CMDQ_SIZE 0x60 #define CMDQ_SIZE 0x3f @@ -180,6 +181,7 @@ struct mtk_dsi_driver_data { bool has_shadow_ctl; bool has_size_ctl; bool cmdq_long_packet_ctl; + bool support_per_frame_lp; }; struct mtk_dsi { @@ -516,6 +518,103 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi) (vm->hactive * dsi_tmp_buf_bpp + 2) % dsi->lanes; } + if (dsi->driver_data->support_per_frame_lp) { + unsigned int lpx = 0, da_hs_exit = 0, da_hs_prep = 0, da_hs_trail = 0; + unsigned int da_hs_zero = 0, ps_wc = 0, hs_vb_ps_wc = 0; + u32 bllp_wc, bllp_en, v_active_roundup, hstx_cklp_wc; + u32 hstx_cklp_wc_max, hstx_cklp_wc_min; + + da_hs_trail = (readl(dsi->regs + DSI_PHY_TIMECON0) >> 24) & 0xff; + bllp_en = (readl(dsi->regs + DSI_TXRX_CTRL) >> 7) & 0x1; + if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { + horizontal_sync_active_byte = + (vm->hsync_len * dsi_tmp_buf_bpp - 10); + horizontal_backporch_byte = + (vm->hback_porch * dsi_tmp_buf_bpp - 10); + horizontal_frontporch_byte = + (vm->hfront_porch * dsi_tmp_buf_bpp - 12); + + ps_wc = readl(dsi->regs + DSI_PSCTRL) & 0x7fff; + v_active_roundup = (32 + horizontal_sync_active_byte + + horizontal_backporch_byte + ps_wc + + horizontal_frontporch_byte) % dsi->lanes; + if (v_active_roundup) + horizontal_backporch_byte = horizontal_backporch_byte + + dsi->lanes - v_active_roundup; + hstx_cklp_wc_min = (DIV_ROUND_UP((12 + 2 + 4 + + horizontal_sync_active_byte), dsi->lanes) + da_hs_trail + 1) + * dsi->lanes / 6 - 1; + hstx_cklp_wc_max = (DIV_ROUND_UP((20 + 6 + 4 + + horizontal_sync_active_byte + horizontal_backporch_byte + + ps_wc), dsi->lanes) + da_hs_trail + 1) * dsi->lanes / 6 - 1; + } else { + horizontal_sync_active_byte = vm->hsync_len * dsi_tmp_buf_bpp - 4; + + horizontal_backporch_byte = (vm->hback_porch + vm->hsync_len) * + dsi_tmp_buf_bpp - 10; + hstx_cklp_wc_min = (DIV_ROUND_UP(4, dsi->lanes) + da_hs_trail + 1) + * dsi->lanes / 6 - 1; + + if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) { + ps_wc = readl(dsi->regs + DSI_PSCTRL) & 0x7fff; + bllp_wc = readl(dsi->regs + DSI_BLLP_WC) & 0xfff; + horizontal_frontporch_byte = (vm->hfront_porch * + dsi_tmp_buf_bpp - 18); + + v_active_roundup = (28 + horizontal_backporch_byte + ps_wc + + horizontal_frontporch_byte + bllp_wc) % dsi->lanes; + if (v_active_roundup) + horizontal_backporch_byte = horizontal_backporch_byte + + dsi->lanes - v_active_roundup; + if (bllp_en) { + hstx_cklp_wc_max = (DIV_ROUND_UP((16 + 6 + 4 + + horizontal_backporch_byte + bllp_wc + ps_wc), + dsi->lanes) + da_hs_trail + 1) * dsi->lanes / 6 - 1; + } else { + hstx_cklp_wc_max = (DIV_ROUND_UP((12 + 4 + 4 + + horizontal_backporch_byte + bllp_wc + ps_wc), + dsi->lanes) + da_hs_trail + 1) * dsi->lanes / 6 - 1; + } + } else { + ps_wc = readl(dsi->regs + DSI_PSCTRL) & 0x7fff; + horizontal_frontporch_byte = (vm->hfront_porch * + dsi_tmp_buf_bpp - 12); + + v_active_roundup = (22 + horizontal_backporch_byte + ps_wc + + horizontal_frontporch_byte) % dsi->lanes; + if (v_active_roundup) + horizontal_backporch_byte = horizontal_backporch_byte + + dsi->lanes - v_active_roundup; + + hstx_cklp_wc_max = (DIV_ROUND_UP((12 + 4 + 4 + + horizontal_backporch_byte + ps_wc), + dsi->lanes) + da_hs_trail + 1) * dsi->lanes / 6 - 1; + } + } + hstx_cklp_wc = (readl(dsi->regs + DSI_HSTX_CKL_WC) >> 2) & 0x3fff; + if (hstx_cklp_wc <= hstx_cklp_wc_min || + hstx_cklp_wc >= hstx_cklp_wc_max) { + hstx_cklp_wc = (hstx_cklp_wc_max / 2) << 2; + writel(hstx_cklp_wc, dsi->regs + DSI_HSTX_CKL_WC); + } + hstx_cklp_wc = hstx_cklp_wc >> 2; + if (hstx_cklp_wc <= hstx_cklp_wc_min || + hstx_cklp_wc >= hstx_cklp_wc_max) { + DRM_WARN("Wrong setting of hstx_ckl_wc\n"); + } + + lpx = readl(dsi->regs + DSI_PHY_TIMECON0) & 0xff; + da_hs_exit = (readl(dsi->regs + DSI_PHY_TIMECON1) >> 24) & 0xff; + da_hs_prep = (readl(dsi->regs + DSI_PHY_TIMECON0) >> 8) & 0xff; + da_hs_zero = (readl(dsi->regs + DSI_PHY_TIMECON0) >> 16) & 0xff; + ps_wc = readl(dsi->regs + DSI_PSCTRL) & 0x7fff; + hs_vb_ps_wc = ps_wc - + (lpx + da_hs_exit + da_hs_prep + da_hs_zero + 2) + * dsi->lanes; + horizontal_frontporch_byte = (1 << 31) + | (hs_vb_ps_wc << 16) + | (horizontal_frontporch_byte); + } writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC); writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC); writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC); @@ -1246,6 +1345,7 @@ static const struct mtk_dsi_driver_data mt8188_dsi_driver_data = { .has_shadow_ctl = true, .has_size_ctl = true, .cmdq_long_packet_ctl = true, + .support_per_frame_lp = true, }; static const struct of_device_id mtk_dsi_of_match[] = {