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(unknown [10.252.69.73]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20240408024021epsmtip286d2fc1b43e70cfbcc8d723c5a522ebd~ELbblSCu70750907509epsmtip2i; Mon, 8 Apr 2024 02:40:21 +0000 (GMT) From: Seongsu Park To: will@kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, sgsu.park@samsung.com, Leem ChaeHoon , Gyeonggeon Choi , Soomin Cho , DaeRo Lee , kmasta Subject: [PATCH v3] arm64: Cleanup __cpu_set_tcr_t0sz() Date: Mon, 8 Apr 2024 11:40:16 +0900 Message-Id: <20240408024016.490516-1-sgsu.park@samsung.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupnk+LIzCtJLcpLzFFi42LZdlhTX1csUjjNYNUOKYv3y3oYLTa13We0 +LNxN5PFl79LmS02Pb7GanF51xw2i6XXLzJZvG/oYrWY9GMLo0X75xesFi13TB24PdbMW8Po sXPWXXaPTas62Tw2L6n36NuyitHj0NkFrB6fN8kFsEdl22SkJqakFimk5iXnp2TmpdsqeQfH O8ebmhkY6hpaWpgrKeQl5qbaKrn4BOi6ZeYAnaikUJaYUwoUCkgsLlbSt7Mpyi8tSVXIyC8u sVVKLUjJKTAr0CtOzC0uzUvXy0stsTI0MDAyBSpMyM64MeUEW8EXoYpVU9awNDD2CXQxcnJI CJhI/Gq9wN7FyMUhJLCDUeLzg4+MEM4nRonmt7NZIZxvjBK7LsxlhGmZO/8OM0RiL6PEphtz WBBaLl5gBaliE9CSWP2vlx3EFhFwkth/agkbSBGzwCwmiQVH97KAJIQFzCU+z30J1sAioCox 6+RCJhCbV8BaYt2LlawQ6+Ql9h88ywwRF5Q4OfMJWC8zULx562ywMyQE/rJLHL+wlhmiwUXi /PU9LBC2sMSr41vYIWwpiZf9bVB2scS+L2ug6mskHszbA2XbS3Q8awPq5QBaoCmxfpc+xC4+ iXdfe1hBwhICvBIdbUIQprLEua2OEKakxJ8FehAzPCQ+bl8KdryQQKzElC0/2Ccwys1Ccv8s JPfPQli1gJF5FaNYakFxbnpqsWGBCTwik/NzNzGCU6aWxQ7GuW8/6B1iZOJgPMQowcGsJMIb bCqYJsSbklhZlVqUH19UmpNafIjRFBiiE5mlRJPzgUk7ryTe0MTSwMTMyMTC2NLYTEmc98yV slQhgfTEktTs1NSC1CKYPiYOTqkGpl6d2VaCkiq+z959OGTA6m1bkhMi9KD2indqZoOsu9Ht 9wnej1YfiJdeFpHxydR8fZieW9327e+XbO+ZF2h9R7Y69PiG6lvNe75H/TTuPv2/J+ibBKNC uo1Dy5GS6r/fks1k7zo76+6cX7GgLfB5gIhZ97p1fzZnPWeUKWZ03RmQnymuUSQ+4/vT4x0x azcx6T++s6ohluXevpg9ykubtLQVJiquuOdWp++wxeXtP9VP7fs4tvHKXz7DMz9u39L7yuo+ d+VCC04XPWhUivTJvHS4OrU9NqyP1eP/y6mNGVtvstQqFTKeMnlkndnDOi/NRzDCrVTj4Zrs 9vxzji5SMtXMwkYM507NdjHh2qrEUpyRaKjFXFScCAB/ZonRIgQAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrFLMWRmVeSWpSXmKPExsWy7bCSvK5opHCawa8N1hbvl/UwWmxqu89o 8WfjbiaLL3+XMltsenyN1eLyrjlsFkuvX2SyeN/QxWox6ccWRov2zy9YLVrumDpwe6yZt4bR Y+esu+wem1Z1snlsXlLv0bdlFaPHobMLWD0+b5ILYI/isklJzcksSy3St0vgyrgx5QRbwReh ilVT1rA0MPYJdDFyckgImEjMnX+HGcQWEtjNKLFuqjtEXFKi/d1lli5GDiBbWOLw4eIuRi6g kg+MEsf+P2MHqWET0JJY/a8XzBYRcJM4ufUcC0gRs8AiJokvaxvBhgoLmEt8nvuSFcRmEVCV mHVyIROIzStgLbHuxUpWiGXyEvsPnmWGiAtKnJz5hAXEZgaKN2+dzTyBkW8WktQsJKkFjEyr GCVTC4pz03OTDQsM81LL9YoTc4tL89L1kvNzNzGCg1tLYwfjvfn/9A4xMnEwHmKU4GBWEuEN NhVME+JNSaysSi3Kjy8qzUktPsQozcGiJM5rOGN2ipBAemJJanZqakFqEUyWiYNTqoHJcar5 2cde0pJyN7OffikQk78wbZUYxz6xPW9ZWS+XyfxKsTTTv81hyCnt9XbhqkPxqZ+L9FXcYh4y /Zjww19N9ez9w2qBPH+P7Fu97ams7ZU/BSHPGhySJ8WyP/aytl7645DaWa2IpJ5SQdsaz5V+ 4eeTg5z6Ktqn6y8SYoyT6n3S0JU4n/ln4N8EprD0U1X5p5jCvty3jmZgCmY/usNJRFd8evvV p4tXC125orZG+XafyOMcbm7XtUsN1N+pbmoU1e+YLP5PsHSDfavOzGff9eOUdMX2soQc25Ba e2rhKT135cXzViwT4P/UzqD1WuTHWgcrszPTNGZL7eHdoFmzVPz0A/7DNmILV2/PblBiKc5I NNRiLipOBACAVscw3QIAAA== X-CMS-MailID: 20240408024022epcas1p176f9509f6f85fd8dbfa2dd17067a8aee X-Msg-Generator: CA CMS-TYPE: 101P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20240408024022epcas1p176f9509f6f85fd8dbfa2dd17067a8aee References: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240407_194030_547896_9B09B292 X-CRM114-Status: GOOD ( 14.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org In cpu_set_default_tcr_t0sz(), it is an error to shift TCR_T0SZ_OFFSET twice form TCR_T0SZ() and __cpu_set_tcr_t0sz(). Since TCR_T0SZ_OFFSET is 0, no error occurred. We need to clarify whether the parameter of __cpu_set_tcr_t0sz is a shifted value or an unshifted value. We have already shifted the value of t0sz in TCR_T0SZ by TCR_T0SZ_OFFSET. This is necessary for consistency with TCR_T1SZ. Therefore, the parameter of __cpu_set_tcr_t0sz is clarified as a shifted value. Co-developed-by: Leem ChaeHoon Signed-off-by: Leem ChaeHoon Co-developed-by: Gyeonggeon Choi Signed-off-by: Gyeonggeon Choi Co-developed-by: Soomin Cho Signed-off-by: Soomin Cho Co-developed-by: DaeRo Lee Signed-off-by: DaeRo Lee Co-developed-by: kmasta Signed-off-by: kmasta Signed-off-by: Seongsu Park --- v2: - Condition is updated v3: - Commit message is updated - cpu_set_tcr_t0sz macro is added --- arch/arm64/include/asm/mmu_context.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h index c768d16b81a4..fb603ec7f61f 100644 --- a/arch/arm64/include/asm/mmu_context.h +++ b/arch/arm64/include/asm/mmu_context.h @@ -72,15 +72,16 @@ static inline void __cpu_set_tcr_t0sz(unsigned long t0sz) { unsigned long tcr = read_sysreg(tcr_el1); - if ((tcr & TCR_T0SZ_MASK) >> TCR_T0SZ_OFFSET == t0sz) + if ((tcr & TCR_T0SZ_MASK) == t0sz) return; tcr &= ~TCR_T0SZ_MASK; - tcr |= t0sz << TCR_T0SZ_OFFSET; + tcr |= t0sz; write_sysreg(tcr, tcr_el1); isb(); } +#define cpu_set_tcr_t0sz(t0sz) __cpu_set_tcr_t0sz(TCR_T0SZ(t0sz)) #define cpu_set_default_tcr_t0sz() __cpu_set_tcr_t0sz(TCR_T0SZ(vabits_actual)) #define cpu_set_idmap_tcr_t0sz() __cpu_set_tcr_t0sz(idmap_t0sz) @@ -134,7 +135,7 @@ static inline void cpu_install_ttbr0(phys_addr_t ttbr0, unsigned long t0sz) { cpu_set_reserved_ttbr0(); local_flush_tlb_all(); - __cpu_set_tcr_t0sz(t0sz); + cpu_set_tcr_t0sz(t0sz); /* avoid cpu_switch_mm() and its SW-PAN and CNP interactions */ write_sysreg(ttbr0, ttbr0_el1);