| Message ID | 20240408092449.6-1-ian.ray@gehealthcare.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: imx8mp-msc-sm2s: Add i2c{1,6} sda-/scl-gpios | expand |
Hi Ian, > + pinctrl_i2c1_gpio: i2c1gpiogrp { > + fsl,pins = > + <MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c3>, The Sion bit is unnecessary in the GPIO mode so you could pass 0x1c3 instead.
On Mon, Apr 08, 2024 at 08:31:53AM -0300, Fabio Estevam wrote: > > Hi Ian, > > > + pinctrl_i2c1_gpio: i2c1gpiogrp { > > + fsl,pins = > > + <MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c3>, > > The Sion bit is unnecessary in the GPIO mode so you could pass 0x1c3 instead. Thank you -- I will submit a V2. Would 0x1c2 be more correct? From the IMX8MPRM.pdf, it seems that the lowest bit is reserved. Example: 8.2.4.158 SW_PAD_CTL_PAD_GPIO1_IO05 SW PAD Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05).
On Mon, Apr 8, 2024 at 8:44 AM Ian Ray <ian.ray@gehealthcare.com> wrote: > Thank you -- I will submit a V2. > > Would 0x1c2 be more correct? From the IMX8MPRM.pdf, it seems that the > lowest bit is reserved. Example: 8.2.4.158 SW_PAD_CTL_PAD_GPIO1_IO05 > SW PAD Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05). Yes, good catch. It is better not to write to the reserved bit 0, so 0x1c2 is preferred.
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s.dtsi index 61c2a63efc6d..7e4327084d26 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s.dtsi @@ -200,8 +200,11 @@ ethphy1: ethernet-phy@1 { }; &i2c1 { - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; clock-frequency = <400000>; status = "okay"; @@ -241,8 +244,11 @@ &i2c5 { }; &i2c6 { - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c6>; + pinctrl-1 = <&pinctrl_i2c6_gpio>; + scl-gpios = <&gpio3 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; clock-frequency = <400000>; status = "okay"; @@ -606,6 +612,12 @@ pinctrl_i2c1: i2c1grp { <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3>; }; + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = + <MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c3>, + <MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c3>; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3>, @@ -636,6 +648,12 @@ pinctrl_i2c6: i2c6grp { <MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c3>; }; + pinctrl_i2c6_gpio: i2c5gpiogrp { + fsl,pins = + <MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x400001c3>, + <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x400001c3>; + }; + pinctrl_lcd0_backlight: lcd0-backlightgrp { fsl,pins = <MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x41>;
Add i2c{1,6} sda-/scl-gpios with the corresponding pinmux entries. Signed-off-by: Ian Ray <ian.ray@gehealthcare.com> --- .../boot/dts/freescale/imx8mp-msc-sm2s.dtsi | 22 +++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-)