From patchwork Thu Apr 11 14:36:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe ROULLIER X-Patchwork-Id: 13626079 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 250FAC001CC for ; Thu, 11 Apr 2024 14:39:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=HVJLJMkJh/dcoeok0AA1okvF0/RX6oxcnYSPu5AUr4U=; b=Kx6jaBNBmE2qXX hMzQV9wu/jTfUR+NhOl05BDGMXSP6FlOrIRKCfXI5AnC3AqUyZTG8bdp6OhaNIpMyQ8XrRhWr2KcA BedXgAf6R2seL2LfuszpqcWiWO2EchYJKgvkGgilVwYFD68GEjWsFiGSiNd1+dEyMiB45MC9Rt3d0 zQFt0xC4yNDO8n4shiAuDfU31Wi6fRWBnzOvJY6s2QE0XKLRhEYMVP0T6bPx0yt+AlhfjA55w2Riz KKB6T5TlW3MJd3ZHdjCDkISI/HNxRJtAn33TvjkhiDvvSUZwaq6LCG34ZSpAjkcVdsRuBjrBhEy6W FohgTpLiaYtBiI7wV+lw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1ruvZr-0000000CUYG-2s83; Thu, 11 Apr 2024 14:38:59 +0000 Received: from mx07-00178001.pphosted.com ([185.132.182.106]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1ruvZj-0000000CUR4-0zI3 for linux-arm-kernel@lists.infradead.org; Thu, 11 Apr 2024 14:38:53 +0000 Received: from pps.filterd (m0241204.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 43B8nFV0029043; Thu, 11 Apr 2024 16:38:36 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=pdiOg0qMVK3K8F6mkd9yI3FRY3kP3X2qeN1i6q/LFAs=; b=6R YrOvsA8Cfo7AMuhHFFuZUxg4zvvvrIFz2P5I1DfVUpZwhq8VHwmJGSmI7ehstsP7 DREk6dLHmWJ23xTRbZ571qdwrB46tGvpFUX9xrSjZ39knWWgx4iLuKUPUKVKda8s pqbIj/3fx9ETV0p5twbAR91kcAxxvtxPLUwdTfhlzSMuJvBp5vM15lY9Dti0bQLg 3jwt1wJHtKLxTW1H9KfVfCdsQpmP5WXkvP+qflgGkOSPS4nbMh70C6oUwjAb4A16 LbbxlgYujgZ7nLEvK0X2E6IkdZCjjveHplsuy7+DVp0qHscYfprkQjY4oO/1yBnE aCgWVdOrCfd/hfrYpMaQ== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3xawqy5ds5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 11 Apr 2024 16:38:35 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 64D8A40045; Thu, 11 Apr 2024 16:38:30 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 892C4216821; Thu, 11 Apr 2024 16:37:22 +0200 (CEST) Received: from localhost (10.48.86.106) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 11 Apr 2024 16:37:22 +0200 From: Christophe Roullier To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier CC: , , , , Subject: [PATCH 01/11] dt-bindings: net: add STM32MP13 compatible in documentation for stm32 Date: Thu, 11 Apr 2024 16:36:48 +0200 Message-ID: <20240411143658.1049706-2-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240411143658.1049706-1-christophe.roullier@foss.st.com> References: <20240411143658.1049706-1-christophe.roullier@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.48.86.106] X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-11_08,2024-04-09_01,2023-05-22_02 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240411_073851_653904_579E1196 X-CRM114-Status: GOOD ( 12.50 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org New STM32 SOC have 2 GMACs instances. GMAC IP version is SNPS 4.20. Signed-off-by: Christophe Roullier --- .../devicetree/bindings/net/stm32-dwmac.yaml | 80 +++++++++++++++++-- 1 file changed, 72 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml index 857d58949b029..20f58eff6e6f9 100644 --- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml @@ -22,18 +22,17 @@ select: enum: - st,stm32-dwmac - st,stm32mp1-dwmac + - st,stm32mp13-dwmac required: - compatible -allOf: - - $ref: snps,dwmac.yaml# - properties: compatible: oneOf: - items: - enum: - st,stm32mp1-dwmac + - st,stm32mp13-dwmac - const: snps,dwmac-4.20a - items: - enum: @@ -74,13 +73,16 @@ properties: st,syscon: $ref: /schemas/types.yaml#/definitions/phandle-array - items: - - items: - - description: phandle to the syscon node which encompases the glue register - - description: offset of the control register description: Should be phandle/offset pair. The phandle to the syscon node which - encompases the glue register, and the offset of the control register + encompases the glue register, the offset of the control register and + the mask to set bitfield in control register + items: + minItems: 2 + items: + - description: phandle to the syscon node which encompases the glue register + - description: offset of the control register + - description: field to set mask in register st,ext-phyclk: description: @@ -108,6 +110,34 @@ required: unevaluatedProperties: false +allOf: + - $ref: snps,dwmac.yaml# + - if: + properties: + compatible: + contains: + enum: + - st,stm32mp1-dwmac + - st,stm32-dwmac + then: + properties: + st,syscon: + items: + minItems: 2 + + - if: + properties: + compatible: + contains: + enum: + - st,stm32mp13-dwmac + then: + properties: + st,syscon: + items: + minItems: 3 + + examples: - | #include @@ -168,3 +198,37 @@ examples: snps,pbl = <8>; phy-mode = "mii"; }; + + - | + #include + #include + #include + #include + //Example 4 + ethernet3: ethernet@5800a000 { + compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a"; + reg = <0x5800a000 0x2000>; + reg-names = "stmmaceth"; + interrupts-extended = <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, + <&exti 68 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", + "eth_wake_irq"; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", + "eth-ck", + "ptp_ref", + "ethstp"; + clocks = <&rcc ETHMAC>, + <&rcc ETHTX>, + <&rcc ETHRX>, + <&rcc ETHCK_K>, + <&rcc ETHPTP_K>, + <&rcc ETHSTP>; + st,syscon = <&syscfg 0x4 0xff0000>; + snps,mixed-burst; + snps,pbl = <2>; + snps,axi-config = <&stmmac_axi_config_1>; + snps,tso; + phy-mode = "rmii"; + };