@@ -42,6 +42,9 @@
#define NUM_COUNTERS 11
#define CYCLES_COUNTER 0
+#define CONFIG_EVENT GENMASK(7, 0)
+#define CONFIG_COUNTER GENMASK(15, 8)
+
#define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu)
#define DDR_PERF_DEV_NAME "imx9_ddr"
@@ -339,8 +342,10 @@ static void ddr_perf_counter_local_config(struct ddr_pmu *pmu, int config,
int counter, bool enable)
{
u32 ctrl_a;
+ int event;
ctrl_a = readl_relaxed(pmu->base + PMLCA(counter));
+ event = FIELD_GET(CONFIG_EVENT, config);
if (enable) {
ctrl_a |= PMLCA_FC;
@@ -352,7 +357,7 @@ static void ddr_perf_counter_local_config(struct ddr_pmu *pmu, int config,
ctrl_a &= ~PMLCA_FC;
ctrl_a |= PMLCA_CE;
ctrl_a &= ~FIELD_PREP(PMLCA_EVENT, 0x7F);
- ctrl_a |= FIELD_PREP(PMLCA_EVENT, (config & 0x000000FF));
+ ctrl_a |= FIELD_PREP(PMLCA_EVENT, event);
writel(ctrl_a, pmu->base + PMLCA(counter));
} else {
/* Freeze counter. */
@@ -366,8 +371,8 @@ static void ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg, int cfg1, int
u32 pmcfg1, pmcfg2;
int event, counter;
- event = cfg & 0x000000FF;
- counter = (cfg & 0x0000FF00) >> 8;
+ event = FIELD_GET(CONFIG_EVENT, cfg);
+ counter = FIELD_GET(CONFIG_COUNTER, cfg);
pmcfg1 = readl_relaxed(pmu->base + PMCFG1);
@@ -469,7 +474,7 @@ static int ddr_perf_event_add(struct perf_event *event, int flags)
int cfg2 = event->attr.config2;
int counter;
- counter = (cfg & 0x0000FF00) >> 8;
+ counter = FIELD_GET(CONFIG_COUNTER, cfg);
pmu->events[counter] = event;
pmu->active_events++;