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Mon, 15 Apr 2024 00:54:20 -0700 (PDT) Date: Mon, 15 Apr 2024 09:54:14 +0200 In-Reply-To: <20240415075412.2347624-4-ardb+git@google.com> Mime-Version: 1.0 References: <20240415075412.2347624-4-ardb+git@google.com> X-Developer-Key: i=ardb@kernel.org; a=openpgp; fpr=F43D03328115A198C90016883D200E9CA6329909 X-Developer-Signature: v=1; a=openpgp-sha256; l=858; i=ardb@kernel.org; h=from:subject; bh=ODo4vOYSSTd3CKdVF9qBZxLUUnytPQ0BotDws5LU5Tk=; b=owGbwMvMwCFmkMcZplerG8N4Wi2JIU3mrlrC1+JD0mk/vDmPJcvumWnr2vBl2+1kU74HjQem1 u+y/Leoo5SFQYyDQVZMkUVg9t93O09PlKp1niULM4eVCWQIAxenAExEzYGR4WrSUc56D5X3e+Ns GX0jF5+5Oml1kuPFxqj8fXzeJqax8xn+qQtWKfCut17rf25L0pYH98UMyv4kNE2w9Yrb7c11N3Q NAwA= X-Mailer: git-send-email 2.44.0.683.g7961c838ac-goog Message-ID: <20240415075412.2347624-5-ardb+git@google.com> Subject: [PATCH 1/2] arm64/head: Drop unnecessary pre-disable-MMU workaround From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org Cc: Ard Biesheuvel , Catalin Marinas , Will Deacon , Marc Zyngier , Mark Rutland X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240415_005424_953801_E91CFA0E X-CRM114-Status: GOOD ( 10.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Ard Biesheuvel The Falkor erratum that results in the need for an ISB before clearing the M bit in SCTLR_ELx only applies to execution at exception level x, and so the workaround is not needed when disabling the EL1 MMU while running at EL2. Signed-off-by: Ard Biesheuvel Acked-by: Marc Zyngier Acked-by: Mark Rutland --- arch/arm64/kernel/head.S | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 06234c3a15f3..b8bbd72cb194 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -323,13 +323,11 @@ SYM_INNER_LABEL(init_el2, SYM_L_LOCAL) cbz x0, 2f /* Set a sane SCTLR_EL1, the VHE way */ - pre_disable_mmu_workaround msr_s SYS_SCTLR_EL12, x1 mov x2, #BOOT_CPU_FLAG_E2H b 3f 2: - pre_disable_mmu_workaround msr sctlr_el1, x1 mov x2, xzr 3: