| Message ID | 20240425174519.1.I443a218decda670093bc621165e3052db14d4c02@changeid (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: st: add power domain on stm32mp25 | expand |
Hello Patrick On 4/25/24 17:45, Patrick Delaunay wrote: > Add power domains on STM32MP25x SoC for supported low power modes: > - CPU_PD0/1: domain for idle of each core Cortex A35 (CStop) > - CLUSTER_PD: D1 domain with Stop1 and LP-Stop1 modes support when > the Cortex A35 cluster and each device assigned to CPU1=CA35 > are deactivated > - RET_PD: D1 domain retention (VDDCore is reduced) to support > the LPLV-Stop1 mode > > Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> > --- > Applied on stm32-next. Thanks!! Alex > arch/arm64/boot/dts/st/stm32mp251.dtsi | 16 ++++++++++++++++ > arch/arm64/boot/dts/st/stm32mp253.dtsi | 9 +++++++++ > 2 files changed, 25 insertions(+) > > diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi > index af1444bf9442..4beb0a0bef4f 100644 > --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi > +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi > @@ -18,6 +18,8 @@ cpu0: cpu@0 { > device_type = "cpu"; > reg = <0>; > enable-method = "psci"; > + power-domains = <&CPU_PD0>; > + power-domain-names = "psci"; > }; > }; > > @@ -104,6 +106,20 @@ intc: interrupt-controller@4ac00000 { > psci { > compatible = "arm,psci-1.0"; > method = "smc"; > + > + CPU_PD0: power-domain-cpu0 { > + #power-domain-cells = <0>; > + power-domains = <&CLUSTER_PD>; > + }; > + > + CLUSTER_PD: power-domain-cluster { > + #power-domain-cells = <0>; > + power-domains = <&RET_PD>; > + }; > + > + RET_PD: power-domain-retention { > + #power-domain-cells = <0>; > + }; > }; > > timer { > diff --git a/arch/arm64/boot/dts/st/stm32mp253.dtsi b/arch/arm64/boot/dts/st/stm32mp253.dtsi > index af48e82efe8a..79c02ef2e51e 100644 > --- a/arch/arm64/boot/dts/st/stm32mp253.dtsi > +++ b/arch/arm64/boot/dts/st/stm32mp253.dtsi > @@ -12,6 +12,8 @@ cpu1: cpu@1 { > device_type = "cpu"; > reg = <1>; > enable-method = "psci"; > + power-domains = <&CPU_PD1>; > + power-domain-names = "psci"; > }; > }; > > @@ -20,4 +22,11 @@ arm-pmu { > <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; > interrupt-affinity = <&cpu0>, <&cpu1>; > }; > + > + psci { > + CPU_PD1: power-domain-cpu1 { > + #power-domain-cells = <0>; > + power-domains = <&CLUSTER_PD>; > + }; > + }; > };
diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index af1444bf9442..4beb0a0bef4f 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -18,6 +18,8 @@ cpu0: cpu@0 { device_type = "cpu"; reg = <0>; enable-method = "psci"; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; }; }; @@ -104,6 +106,20 @@ intc: interrupt-controller@4ac00000 { psci { compatible = "arm,psci-1.0"; method = "smc"; + + CPU_PD0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + + CLUSTER_PD: power-domain-cluster { + #power-domain-cells = <0>; + power-domains = <&RET_PD>; + }; + + RET_PD: power-domain-retention { + #power-domain-cells = <0>; + }; }; timer { diff --git a/arch/arm64/boot/dts/st/stm32mp253.dtsi b/arch/arm64/boot/dts/st/stm32mp253.dtsi index af48e82efe8a..79c02ef2e51e 100644 --- a/arch/arm64/boot/dts/st/stm32mp253.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp253.dtsi @@ -12,6 +12,8 @@ cpu1: cpu@1 { device_type = "cpu"; reg = <1>; enable-method = "psci"; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; }; }; @@ -20,4 +22,11 @@ arm-pmu { <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; interrupt-affinity = <&cpu0>, <&cpu1>; }; + + psci { + CPU_PD1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + }; + }; };
Add power domains on STM32MP25x SoC for supported low power modes: - CPU_PD0/1: domain for idle of each core Cortex A35 (CStop) - CLUSTER_PD: D1 domain with Stop1 and LP-Stop1 modes support when the Cortex A35 cluster and each device assigned to CPU1=CA35 are deactivated - RET_PD: D1 domain retention (VDDCore is reduced) to support the LPLV-Stop1 mode Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 16 ++++++++++++++++ arch/arm64/boot/dts/st/stm32mp253.dtsi | 9 +++++++++ 2 files changed, 25 insertions(+)