| Message ID | 20240426125707.585269-2-christophe.roullier@foss.st.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Series to deliver Ethernets for STM32MP13 | expand |
On 4/26/24 2:56 PM, Christophe Roullier wrote: > New STM32 SOC Which New STM32 SoC is that ? Please add type/model/... > have 2 GMACs instances. > GMAC IP version is SNPS 4.20. The commit message should describe what does this patch do, and why does it do so, something like: " Document support for STM32MP13xx. This SoC contains two instances of DWMAC 4.20 IP. Because this is <somehow special>, document <some difference>. " [...]
On Fri, Apr 26, 2024 at 02:56:57PM +0200, Christophe Roullier wrote: > New STM32 SOC have 2 GMACs instances. > GMAC IP version is SNPS 4.20. > > Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com> > --- > .../devicetree/bindings/net/stm32-dwmac.yaml | 76 ++++++++++++++++--- > 1 file changed, 67 insertions(+), 9 deletions(-) > > diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml > index f2714b5b6cf4..b901a432dfa9 100644 > --- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml > +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml > @@ -22,18 +22,17 @@ select: > enum: > - st,stm32-dwmac > - st,stm32mp1-dwmac > + - st,stm32mp13-dwmac > required: > - compatible > > -allOf: > - - $ref: snps,dwmac.yaml# > - > properties: > compatible: > oneOf: > - items: > - enum: > - st,stm32mp1-dwmac > + - st,stm32mp13-dwmac > - const: snps,dwmac-4.20a > - items: > - enum: > @@ -74,13 +73,16 @@ properties: > > st,syscon: > $ref: /schemas/types.yaml#/definitions/phandle-array > + description: Why do you move the location of 'description'? It just increases the diff. My preference is description is either 1st or last and not in the middle. > + Should be phandle/offset pair. The phandle to the syscon node which > + encompases the glue register, the offset of the control register and > + the mask to set bitfield in control register > items: > - - items: > + - minItems: 2 > + items: > - description: phandle to the syscon node which encompases the glue register > - description: offset of the control register > - description: > - Should be phandle/offset pair. The phandle to the syscon node which > - encompases the glue register, and the offset of the control register > + - description: field to set mask in register > > st,eth-clk-sel: > description: > @@ -105,12 +107,38 @@ required: > > unevaluatedProperties: false > > +allOf: > + - $ref: snps,dwmac.yaml# > + - if: > + properties: > + compatible: > + contains: > + enum: > + - st,stm32mp1-dwmac > + - st,stm32-dwmac > + then: > + properties: > + st,syscon: > + items: > + maxItems: 2 > + > + - if: > + properties: > + compatible: > + contains: > + enum: > + - st,stm32mp13-dwmac > + then: > + properties: > + st,syscon: > + items: > + minItems: 3 > + maxItems: 3 Just minItems is needed. > + > examples: > - | > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/clock/stm32mp1-clks.h> > - #include <dt-bindings/reset/stm32mp1-resets.h> > - #include <dt-bindings/mfd/stm32h7-rcc.h> > //Example 1 > ethernet0: ethernet@5800a000 { > compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; > @@ -165,3 +193,33 @@ examples: > snps,pbl = <8>; > phy-mode = "mii"; > }; > + > + - | > + //Example 4 I don't think it is worth a whole new example just for 1 property difference. > + ethernet3: ethernet@5800a000 { > + compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a"; > + reg = <0x5800a000 0x2000>; > + reg-names = "stmmaceth"; > + interrupts-extended = <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, > + <&exti 68 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "macirq", > + "eth_wake_irq"; > + clock-names = "stmmaceth", > + "mac-clk-tx", > + "mac-clk-rx", > + "eth-ck", > + "ptp_ref", > + "ethstp"; > + clocks = <&rcc ETHMAC>, > + <&rcc ETHTX>, > + <&rcc ETHRX>, > + <&rcc ETHCK_K>, > + <&rcc ETHPTP_K>, > + <&rcc ETHSTP>; > + st,syscon = <&syscfg 0x4 0xff0000>; > + snps,mixed-burst; > + snps,pbl = <2>; > + snps,axi-config = <&stmmac_axi_config_1>; > + snps,tso; > + phy-mode = "rmii"; > + }; > -- > 2.25.1 >
diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml index f2714b5b6cf4..b901a432dfa9 100644 --- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml @@ -22,18 +22,17 @@ select: enum: - st,stm32-dwmac - st,stm32mp1-dwmac + - st,stm32mp13-dwmac required: - compatible -allOf: - - $ref: snps,dwmac.yaml# - properties: compatible: oneOf: - items: - enum: - st,stm32mp1-dwmac + - st,stm32mp13-dwmac - const: snps,dwmac-4.20a - items: - enum: @@ -74,13 +73,16 @@ properties: st,syscon: $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Should be phandle/offset pair. The phandle to the syscon node which + encompases the glue register, the offset of the control register and + the mask to set bitfield in control register items: - - items: + - minItems: 2 + items: - description: phandle to the syscon node which encompases the glue register - description: offset of the control register - description: - Should be phandle/offset pair. The phandle to the syscon node which - encompases the glue register, and the offset of the control register + - description: field to set mask in register st,eth-clk-sel: description: @@ -105,12 +107,38 @@ required: unevaluatedProperties: false +allOf: + - $ref: snps,dwmac.yaml# + - if: + properties: + compatible: + contains: + enum: + - st,stm32mp1-dwmac + - st,stm32-dwmac + then: + properties: + st,syscon: + items: + maxItems: 2 + + - if: + properties: + compatible: + contains: + enum: + - st,stm32mp13-dwmac + then: + properties: + st,syscon: + items: + minItems: 3 + maxItems: 3 + examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/stm32mp1-clks.h> - #include <dt-bindings/reset/stm32mp1-resets.h> - #include <dt-bindings/mfd/stm32h7-rcc.h> //Example 1 ethernet0: ethernet@5800a000 { compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; @@ -165,3 +193,33 @@ examples: snps,pbl = <8>; phy-mode = "mii"; }; + + - | + //Example 4 + ethernet3: ethernet@5800a000 { + compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a"; + reg = <0x5800a000 0x2000>; + reg-names = "stmmaceth"; + interrupts-extended = <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, + <&exti 68 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", + "eth_wake_irq"; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", + "eth-ck", + "ptp_ref", + "ethstp"; + clocks = <&rcc ETHMAC>, + <&rcc ETHTX>, + <&rcc ETHRX>, + <&rcc ETHCK_K>, + <&rcc ETHPTP_K>, + <&rcc ETHSTP>; + st,syscon = <&syscfg 0x4 0xff0000>; + snps,mixed-burst; + snps,pbl = <2>; + snps,axi-config = <&stmmac_axi_config_1>; + snps,tso; + phy-mode = "rmii"; + };
New STM32 SOC have 2 GMACs instances. GMAC IP version is SNPS 4.20. Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com> --- .../devicetree/bindings/net/stm32-dwmac.yaml | 76 ++++++++++++++++--- 1 file changed, 67 insertions(+), 9 deletions(-)