| Message ID | 20240503153329.3906030-1-l.stach@pengutronix.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | clk: rockchip: rk3568: Add PLL rate for 724 MHz | expand |
On Fri, 3 May 2024 17:33:29 +0200, Lucas Stach wrote: > This rate allows to provide a low-jitter 72,4 MHz pixelclock > for a custom eDP panel from the VPLL. > > Applied, thanks! [1/1] clk: rockchip: rk3568: Add PLL rate for 724 MHz commit: f513991b69885025995dcb4ca75d2ee7261e1273 Best regards,
diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c index 8cb21d10beca..292f2ef32958 100644 --- a/drivers/clk/rockchip/clk-rk3568.c +++ b/drivers/clk/rockchip/clk-rk3568.c @@ -64,6 +64,7 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = { RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0), RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0), + RK3036_PLL_RATE(724000000, 3, 181, 2, 1, 1, 0), RK3036_PLL_RATE(700000000, 3, 350, 4, 1, 1, 0), RK3036_PLL_RATE(696000000, 1, 116, 4, 1, 1, 0), RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0),
This rate allows to provide a low-jitter 72,4 MHz pixelclock for a custom eDP panel from the VPLL. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> --- drivers/clk/rockchip/clk-rk3568.c | 1 + 1 file changed, 1 insertion(+)