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EdgeLock Enclave has a hardware limitation of restricted access to DDR address: 0x80000000 to 0xAFFFFFFF, so reserve 1MB of DDR memory region from 0x80000000. Signed-off-by: Pankaj Gupta --- arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 17 ++++++++++++++++- arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 18 ++++++++++++++++-- 2 files changed, 32 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts index 69dd8e31027c..bac08297ef68 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright 2021 NXP + * Copyright 2021, 2024 NXP */ /dts-v1/; @@ -19,6 +19,17 @@ memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ele_reserved: ele-reserved@90000000 { + compatible = "shared-dma-pool"; + reg = <0 0x90000000 0 0x100000>; + no-map; + }; + }; reserved-memory { #address-cells = <2>; @@ -146,6 +157,10 @@ &usdhc0 { status = "okay"; }; +&ele_if0 { + memory-region = <&ele_reserved>; +}; + &fec { pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_enet>; diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index c4a0082f30d3..fc00f05fa166 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright 2021 NXP + * Copyright 2021, 2024 NXP */ #include @@ -152,7 +152,7 @@ sosc: clock-sosc { #clock-cells = <0>; }; - sram@2201f000 { + sram0: sram@2201f000 { compatible = "mmio-sram"; reg = <0x0 0x2201f000 0x0 0x1000>; @@ -184,6 +184,20 @@ scmi_sensor: protocol@15 { #thermal-sensor-cells = <1>; }; }; + + ele { + compatible = "fsl,imx8ulp-ele"; + #address-cells = <1>; + #size-cells = <0>; + + ele_if0: ele-if@0 { + reg = <0x0>; + mbox-names = "tx", "rx"; + mboxes = <&s4muap 0 0>, + <&s4muap 1 0>; + sram = <&sram0>; + }; + }; }; cm33: remoteproc-cm33 {