| Message ID | 20240524090514.152727-7-s-vadapalli@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add PCIe and USB device-tree support for J722S | expand |
On 24/05/2024 12:05, Siddharth Vadapalli wrote: > The Serdes1 instance of Serdes on TI's J722S SoC is a 1 Lane Serdes with > the WIZ1 instance of the WIZ wrapper used for configuring the Serdes. > > Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> > --- > Current patch is v1. No changelog. > > arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 36 +++++++++++++++++++++++ > 1 file changed, 36 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi > index 48b77e476c77..19a7e8413ad2 100644 > --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi > @@ -60,6 +60,42 @@ serdes0: serdes@f000000 { > }; > }; > > + serdes_wiz1: phy@f010000 { > + compatible = "ti,am64-wiz-10g"; > + ranges = <0x0f010000 0x0 0x0f010000 0x00010000>; > + #address-cells = <1>; > + #size-cells = <1>; > + power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; > + clocks = <&k3_clks 280 0>, <&k3_clks 280 1>, <&serdes_refclk>; > + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; > + num-lanes = <1>; > + #reset-cells = <1>; > + #clock-cells = <1>; > + > + assigned-clocks = <&k3_clks 280 1>; > + assigned-clock-parents = <&k3_clks 280 5>; > + > + serdes1: serdes@f010000 { > + compatible = "ti,j721e-serdes-10g"; > + reg = <0x0f010000 0x00010000>; > + reg-names = "torrent_phy"; > + resets = <&serdes_wiz1 0>; > + reset-names = "torrent_reset"; > + clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, > + <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>; > + clock-names = "refclk", "phy_en_refclk"; > + assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, > + <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>, > + <&serdes_wiz1 TI_WIZ_REFCLK_DIG>; > + assigned-clock-parents = <&k3_clks 280 1>, > + <&k3_clks 280 1>, > + <&k3_clks 280 1>; > + #address-cells = <1>; > + #size-cells = <0>; > + #clock-cells = <1>; > + }; > + }; > + Any particular reason to split addition of various nodes in the k3-j722s-main file? I think all k3-j722s-main.dtsi additions can be in one patch. > usbss1: usb@f920000 { > compatible = "ti,j721e-usb"; > reg = <0x00 0x0f920000 0x00 0x100>;
On Tue, May 28, 2024 at 03:24:44PM +0300, Roger Quadros wrote: [...] > > + #size-cells = <0>; > > + #clock-cells = <1>; > > + }; > > + }; > > + > > Any particular reason to split addition of various nodes in the k3-j722s-main file? > I think all k3-j722s-main.dtsi additions can be in one patch. The intent was to preserve patch ownership from v2. I will combine them in the v4. Regards, Siddharth.
diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi index 48b77e476c77..19a7e8413ad2 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -60,6 +60,42 @@ serdes0: serdes@f000000 { }; }; + serdes_wiz1: phy@f010000 { + compatible = "ti,am64-wiz-10g"; + ranges = <0x0f010000 0x0 0x0f010000 0x00010000>; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 280 0>, <&k3_clks 280 1>, <&serdes_refclk>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; + num-lanes = <1>; + #reset-cells = <1>; + #clock-cells = <1>; + + assigned-clocks = <&k3_clks 280 1>; + assigned-clock-parents = <&k3_clks 280 5>; + + serdes1: serdes@f010000 { + compatible = "ti,j721e-serdes-10g"; + reg = <0x0f010000 0x00010000>; + reg-names = "torrent_phy"; + resets = <&serdes_wiz1 0>; + reset-names = "torrent_reset"; + clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>; + clock-names = "refclk", "phy_en_refclk"; + assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz1 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents = <&k3_clks 280 1>, + <&k3_clks 280 1>, + <&k3_clks 280 1>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + }; + }; + usbss1: usb@f920000 { compatible = "ti,j721e-usb"; reg = <0x00 0x0f920000 0x00 0x100>;
The Serdes1 instance of Serdes on TI's J722S SoC is a 1 Lane Serdes with the WIZ1 instance of the WIZ wrapper used for configuring the Serdes. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> --- Current patch is v1. No changelog. arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 36 +++++++++++++++++++++++ 1 file changed, 36 insertions(+)