From patchwork Fri May 31 15:07:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amelie Delaunay X-Patchwork-Id: 13681799 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 06D11C25B7E for ; Fri, 31 May 2024 15:08:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=HwLXPSTDKlRmAT0H5t4I6TGHrHq+0MDbJ6qoLXBt9R0=; b=4uZUGFb2FiPYBJ RU3/yqg4GlnJxPXNWVyFjAAM6zr5mvUPkCwS66D1y4oOQC7zIa4lPVItpVFU4F9ZfVjnKwNSspvXy rsBAKIX+kdlU04fsy+H1qqTbTyWefjAsGnV9tgUv6cY6QhZRiFS3bQc5ieG0nPC943P1HhsrbrL94 5sZv4Zek59RtYuzFEPAgA9HcrLSwQcMN1hrVPzgx2MiEVFBOL0pMmrnE7YZWqEQZ5uptnN7hL4g+u y52IKQ5I3IXl0/nzhGWYwOB0VfJ3ncH7GE8i4KIbimGwEoJ+XIYwsjxqBJcP8Kf5Zld3uuH9pah9m vi4zw0hrIo/+aP04W/yA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sD3s1-0000000Ac4M-2DsK; Fri, 31 May 2024 15:08:41 +0000 Received: from mx08-00178001.pphosted.com ([91.207.212.93] helo=mx07-00178001.pphosted.com) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sD3rq-0000000Ac1a-3Jfq for linux-arm-kernel@lists.infradead.org; Fri, 31 May 2024 15:08:32 +0000 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 44VCl3hH007215; Fri, 31 May 2024 17:08:22 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= 9ZF3jBpvGxEjMOmWl5kYZUL4xPirVkoV+kbkxrvuiGg=; b=wLKDZCNku313z0pU 3yXfx0lUp+S29sEcPomHaUJOleN3nU4EqRws7mlEOlGpMtYA/3UryeVnR7RsNVrr 3qqKYjH5sbnTuaPVsX9YaDCAovK341hxOm9kOANvkoq6VkP3cYU1SIg9cuagJGUS DyqLc7btFAb3VYRbU3H7q5OZ/+d4wfjCblnyH9udxApgdHuu5n3RaYOlgaMF+KfF JeKgYrftglduiw+GSF2GGISVGrITrk/3aF0b+xhPBWGD1Fgs/PpGfoKQgRKvn4xM y1/Fy1FYmRtIP8eYy7sQiSvX6mN4SiUX1dgYM89suy6Qqa3wU1s3qzajIFeF7i1i w80hrg== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3yb9ykd6t1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 31 May 2024 17:08:22 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 1191C40047; Fri, 31 May 2024 17:08:18 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 5FAFD223654; Fri, 31 May 2024 17:07:19 +0200 (CEST) Received: from localhost (10.252.27.179) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 31 May 2024 17:07:19 +0200 From: Amelie Delaunay To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue CC: , , , , , , Amelie Delaunay , Rob Herring Subject: [PATCH v4 04/12] dt-bindings: dma: Document STM32 DMA3 controller bindings Date: Fri, 31 May 2024 17:07:04 +0200 Message-ID: <20240531150712.2503554-5-amelie.delaunay@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240531150712.2503554-1-amelie.delaunay@foss.st.com> References: <20240531150712.2503554-1-amelie.delaunay@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.252.27.179] X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.12.28.16 definitions=2024-05-31_11,2024-05-30_01,2024-05-17_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240531_080831_137063_52BC30D3 X-CRM114-Status: GOOD ( 19.35 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The STM32 DMA3 is a Direct Memory Access controller with different features depending on its hardware configuration. The channels have not the same capabilities, some have a larger FIFO, so their performance is higher. This patch describes STM32 DMA3 bindings, used to select a channel that fits client requirements, and to pre-configure the channel depending on the client needs. Reviewed-by: Rob Herring (Arm) Signed-off-by: Amelie Delaunay --- v3: - add Rob's Reviewed-by after fixing lines length at 80 and useless '|' v2: - DMA controller specific information description has been moved and added as description of #dma-cells property - description has been added to interrupts property specifying the expected format for channel interrupts - compatible has been updated to st,stm32mp25-dma3 (SoC specific) --- .../bindings/dma/stm32/st,stm32-dma3.yaml | 135 ++++++++++++++++++ 1 file changed, 135 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/stm32/st,stm32-dma3.yaml diff --git a/Documentation/devicetree/bindings/dma/stm32/st,stm32-dma3.yaml b/Documentation/devicetree/bindings/dma/stm32/st,stm32-dma3.yaml new file mode 100644 index 000000000000..7fdc44b2e646 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/stm32/st,stm32-dma3.yaml @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/stm32/st,stm32-dma3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 DMA3 Controller + +description: | + The STM32 DMA3 is a direct memory access controller with different features + depending on its hardware configuration. + It is either called LPDMA (Low Power), GPDMA (General Purpose) or HPDMA (High + Performance). + Its hardware configuration registers allow to dynamically expose its features. + + GPDMA and HPDMA support 16 independent DMA channels, while only 4 for LPDMA. + GPDMA and HPDMA support 256 DMA requests from peripherals, 8 for LPDMA. + + Bindings are generic for these 3 STM32 DMA3 configurations. + + DMA clients connected to the STM32 DMA3 controller must use the format + described in "#dma-cells" property description below, using a three-cell + specifier for each channel. + +maintainers: + - Amelie Delaunay + +allOf: + - $ref: /schemas/dma/dma-controller.yaml# + +properties: + compatible: + const: st,stm32mp25-dma3 + + reg: + maxItems: 1 + + interrupts: + minItems: 4 + maxItems: 16 + description: + Should contain all of the per-channel DMA interrupts in ascending order + with respect to the DMA channel index. + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + power-domains: + maxItems: 1 + + "#dma-cells": + const: 3 + description: | + Specifies the number of cells needed to provide DMA controller specific + information. + The first cell is the request line number. + The second cell is a 32-bit mask specifying the DMA channel requirements: + -bit 0-1: The priority level + 0x0: low priority, low weight + 0x1: low priority, mid weight + 0x2: low priority, high weight + 0x3: high priority + -bit 4-7: The FIFO requirement for queuing source/destination transfers + 0x0: no FIFO requirement/any channel can fit + 0x2: FIFO of 8 bytes (2^2+1) + 0x4: FIFO of 32 bytes (2^4+1) + 0x6: FIFO of 128 bytes (2^6+1) + 0x7: FIFO of 256 bytes (2^7+1) + The third cell is a 32-bit mask specifying the DMA transfer requirements: + -bit 0: The source incrementing burst + 0x0: fixed burst + 0x1: contiguously incremented burst + -bit 1: The source allocated port + 0x0: port 0 is allocated to the source transfer + 0x1: port 1 is allocated to the source transfer + -bit 4: The destination incrementing burst + 0x0: fixed burst + 0x1: contiguously incremented burst + -bit 5: The destination allocated port + 0x0: port 0 is allocated to the destination transfer + 0x1: port 1 is allocated to the destination transfer + -bit 8: The type of hardware request + 0x0: burst + 0x1: block + -bit 9: The control mode + 0x0: DMA controller control mode + 0x1: peripheral control mode + -bit 12-13: The transfer complete event mode + 0x0: at block level, transfer complete event is generated at the end + of a block + 0x2: at LLI level, the transfer complete event is generated at the end + of the LLI transfer + including the update of the LLI if any + 0x3: at channel level, the transfer complete event is generated at the + end of the last LLI + +required: + - compatible + - reg + - interrupts + - clocks + - "#dma-cells" + +unevaluatedProperties: false + +examples: + - | + #include + #include + dma-controller@40400000 { + compatible = "st,stm32mp25-dma3"; + reg = <0x40400000 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&rcc CK_BUS_HPDMA1>; + #dma-cells = <3>; + }; +...