diff mbox series

[1/7] arm64: dts: imx8qm: add lvds subsystem

Message ID 20240606-imx8qm-dts-usb-v1-1-565721b64f25@nxp.com (mailing list archive)
State New, archived
Headers show
Series arm64: dts: imx8qm: add subsystem lvds and mipi | expand

Commit Message

Frank Li June 6, 2024, 6:46 p.m. UTC 
Add irqstear, pwm and i2c in lvds subsystem.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi | 231 ++++++++++++++++++++++
 arch/arm64/boot/dts/freescale/imx8qm.dtsi         |   1 +
 2 files changed, 232 insertions(+)

Comments

Peng Fan June 7, 2024, 1:28 a.m. UTC | #1 
> Subject: [PATCH 1/7] arm64: dts: imx8qm: add lvds subsystem
> 
> Add irqstear, pwm and i2c in lvds subsystem.

irqsteer

> 
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi | 231
> ++++++++++++++++++++++
>  arch/arm64/boot/dts/freescale/imx8qm.dtsi         |   1 +
>  2 files changed, 232 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi
> b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi
> new file mode 100644
> index 0000000000000..eb8208cddeaf9
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi
> @@ -0,0 +1,231 @@
> +// SPDX-License-Identifier: GPL-2.0+

GPL-2.0-only and MIT?

> +
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +/{
> +
> +	lvds1_ipg_clk: lvds0_ipg_clk: clock-controller-lvds-ipg {

Two alias name?

> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <24000000>;
> +		clock-output-names = "lvds0_ipg_clk";
> +	};
> +

Regards,
Peng.
Frank Li June 7, 2024, 6:52 p.m. UTC | #2 
On Fri, Jun 07, 2024 at 01:28:35AM +0000, Peng Fan wrote:
> > Subject: [PATCH 1/7] arm64: dts: imx8qm: add lvds subsystem
> > 
> > Add irqstear, pwm and i2c in lvds subsystem.
> 
> irqsteer
> 
> > 
> > Signed-off-by: Frank Li <Frank.Li@nxp.com>
> > ---
> >  arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi | 231
> > ++++++++++++++++++++++
> >  arch/arm64/boot/dts/freescale/imx8qm.dtsi         |   1 +
> >  2 files changed, 232 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi
> > b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi
> > new file mode 100644
> > index 0000000000000..eb8208cddeaf9
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi
> > @@ -0,0 +1,231 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> 
> GPL-2.0-only and MIT?
> 
> > +
> > +/*
> > + * Copyright 2024 NXP
> > + */
> > +
> > +/{
> > +
> > +	lvds1_ipg_clk: lvds0_ipg_clk: clock-controller-lvds-ipg {
> 
> Two alias name?

It is alllowed by dt. link to one fixed 24M clock. of course we can change
lvds1_ipg_clk to lvds0_ipg_clk.

To avoid confuse, I'd better use two name to align node nams.

Frank

> 
> > +		compatible = "fixed-clock";
> > +		#clock-cells = <0>;
> > +		clock-frequency = <24000000>;
> > +		clock-output-names = "lvds0_ipg_clk";
> > +	};
> > +
> 
> Regards,
> Peng.
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi
new file mode 100644
index 0000000000000..eb8208cddeaf9
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi
@@ -0,0 +1,231 @@ 
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright 2024 NXP
+ */
+
+/{
+
+	lvds1_ipg_clk: lvds0_ipg_clk: clock-controller-lvds-ipg {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <24000000>;
+		clock-output-names = "lvds0_ipg_clk";
+	};
+
+	lvds1_subsys: bus@56240000 {
+		compatible = "simple-bus";
+		interrupt-parent = <&irqsteer_lvds0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x56240000 0x0 0x56240000 0x10000>;
+
+		irqsteer_lvds0: interrupt-controller@56240000 {
+			compatible = "fsl,imx-irqsteer";
+			reg = <0x56240000 0x1000>;
+			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			interrupt-parent = <&gic>;
+			#interrupt-cells = <1>;
+			clocks = <&lvds0_lis_lpcg IMX_LPCG_CLK_4>;
+			clock-names = "ipg";
+			power-domains = <&pd IMX_SC_R_LVDS_0>;
+
+			fsl,channel = <0>;
+			fsl,num-irqs = <32>;
+		};
+
+		lvds0_lis_lpcg: clock-controller@56243000 {
+			compatible = "fsl,imx8qxp-lpcg";
+			reg = <0x56243000 0x4>;
+			#clock-cells = <1>;
+			clocks = <&lvds0_ipg_clk>;
+			clock-indices = <IMX_LPCG_CLK_4>;
+			clock-output-names = "lvds0_lis_lpcg_ipg_clk";
+			power-domains = <&pd IMX_SC_R_LVDS_0>;
+		};
+
+		lvds0_pwm_lpcg: clock-controller@5624300c {
+			compatible = "fsl,imx8qxp-lpcg";
+			reg = <0x5624300c 0x4>;
+			#clock-cells = <1>;
+			clocks = <&clk IMX_SC_R_LVDS_0_PWM_0 IMX_SC_PM_CLK_PER>,
+				 <&lvds0_ipg_clk>;
+			clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+			clock-output-names = "lvds0_pwm_lpcg_clk",
+					     "lvds0_pwm_lpcg_ipg_clk";
+			power-domains = <&pd IMX_SC_R_LVDS_0_PWM_0>;
+		};
+
+		lvds0_i2c0_lpcg: clock-controller@56243010 {
+			compatible = "fsl,imx8qxp-lpcg";
+			reg = <0x56243010 0x4>;
+			#clock-cells = <1>;
+			clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>,
+				 <&lvds0_ipg_clk>;
+			clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+			clock-output-names = "lvds0_i2c0_lpcg_clk",
+					     "lvds0_i2c0_lpcg_ipg_clk";
+			power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>;
+		};
+
+		lvds0_i2c1_lpcg: clock-controller@56243014 {
+			compatible = "fsl,imx8qxp-lpcg";
+			reg = <0x56243014 0x4>;
+			#clock-cells = <1>;
+			clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>,
+				 <&lvds0_ipg_clk>;
+			clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+			clock-output-names = "lvds0_i2c1_lpcg_clk",
+					     "lvds0_i2c1_lpcg_ipg_clk";
+			power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>;
+		};
+
+		pwm_lvds0: pwm@56244000 {
+			compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
+			reg = <0x56244000 0x1000>;
+			clocks = <&lvds0_pwm_lpcg IMX_LPCG_CLK_4>,
+				 <&lvds0_pwm_lpcg IMX_LPCG_CLK_0>;
+			clock-names = "ipg", "per";
+			assigned-clocks = <&clk IMX_SC_R_LVDS_0_PWM_0 IMX_SC_PM_CLK_PER>;
+			assigned-clock-rates = <24000000>;
+			#pwm-cells = <3>;
+			power-domains = <&pd IMX_SC_R_LVDS_0_PWM_0>;
+			status = "disabled";
+		};
+
+		i2c0_lvds0: i2c@56246000 {
+			compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+			reg = <0x56246000 0x1000>;
+			interrupts = <8>;
+			clocks = <&lvds0_i2c0_lpcg IMX_LPCG_CLK_0>,
+				 <&lvds0_i2c0_lpcg IMX_LPCG_CLK_4>;
+			clock-names = "per", "ipg";
+			assigned-clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>;
+			assigned-clock-rates = <24000000>;
+			power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>;
+			status = "disabled";
+		};
+
+		i2c1_lvds0: i2c@56247000 {
+			compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+			reg = <0x56247000 0x1000>;
+			interrupts = <9>;
+			clocks = <&lvds0_i2c0_lpcg IMX_LPCG_CLK_0>,
+				 <&lvds0_i2c0_lpcg IMX_LPCG_CLK_4>;
+			clock-names = "per", "ipg";
+			assigned-clocks = <&clk IMX_SC_R_LVDS_0_I2C_0 IMX_SC_PM_CLK_PER>;
+			assigned-clock-rates = <24000000>;
+			power-domains = <&pd IMX_SC_R_LVDS_0_I2C_0>;
+			status = "disabled";
+		};
+	};
+
+	lvds2_subsys: bus@57240000 {
+		compatible = "simple-bus";
+		interrupt-parent = <&irqsteer_lvds1>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x57240000 0x0 0x57240000 0x10000>;
+
+		irqsteer_lvds1: interrupt-controller@57240000 {
+			compatible = "fsl,imx-irqsteer";
+			reg = <0x57240000 0x1000>;
+			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			interrupt-parent = <&gic>;
+			#interrupt-cells = <1>;
+			clocks = <&lvds1_lis_lpcg IMX_LPCG_CLK_4>;
+			clock-names = "ipg";
+			power-domains = <&pd IMX_SC_R_LVDS_1>;
+
+			fsl,channel = <0>;
+			fsl,num-irqs = <32>;
+		};
+
+		lvds1_lis_lpcg: clock-controller@57243000 {
+			compatible = "fsl,imx8qxp-lpcg";
+			reg = <0x57243000 0x4>;
+			#clock-cells = <1>;
+			clocks = <&lvds1_ipg_clk>;
+			clock-indices = <IMX_LPCG_CLK_4>;
+			clock-output-names = "lvds1_lis_lpcg_ipg_clk";
+			power-domains = <&pd IMX_SC_R_LVDS_1>;
+		};
+
+		lvds1_pwm_lpcg: clock-controller@5724300c {
+			compatible = "fsl,imx8qxp-lpcg";
+			reg = <0x5724300c 0x4>;
+			#clock-cells = <1>;
+			clocks = <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>,
+				 <&lvds1_ipg_clk>;
+			clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+			clock-output-names = "lvds1_pwm_lpcg_clk",
+					     "lvds1_pwm_lpcg_ipg_clk";
+			power-domains = <&pd IMX_SC_R_LVDS_1_PWM_0>;
+		};
+
+		lvds1_i2c0_lpcg: clock-controller@57243010 {
+			compatible = "fsl,imx8qxp-lpcg";
+			reg = <0x57243010 0x4>;
+			#clock-cells = <1>;
+			clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>,
+				 <&lvds1_ipg_clk>;
+			clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+			clock-output-names = "lvds1_i2c0_lpcg_clk",
+					     "lvds1_i2c0_lpcg_ipg_clk";
+			power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
+		};
+
+		lvds1_i2c1_lpcg: clock-controller@57243014 {
+			compatible = "fsl,imx8qxp-lpcg";
+			reg = <0x57243014 0x4>;
+			#clock-cells = <1>;
+			clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>,
+				 <&lvds1_ipg_clk>;
+			clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+			clock-output-names = "lvds1_i2c1_lpcg_clk",
+					     "lvds1_i2c1_lpcg_ipg_clk";
+			power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
+		};
+
+		pwm_lvds1: pwm@57244000 {
+			compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
+			reg = <0x57244000 0x1000>;
+			clocks = <&lvds1_pwm_lpcg IMX_LPCG_CLK_4>,
+				 <&lvds1_pwm_lpcg IMX_LPCG_CLK_0>;
+			clock-names = "ipg", "per";
+			assigned-clocks = <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>;
+			assigned-clock-rates = <24000000>;
+			#pwm-cells = <3>;
+			power-domains = <&pd IMX_SC_R_LVDS_1_PWM_0>;
+			status = "disabled";
+		};
+
+		i2c0_lvds1: i2c@57246000 {
+			compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+			reg = <0x57246000 0x1000>;
+			interrupts = <8>;
+			clocks = <&lvds1_i2c0_lpcg IMX_LPCG_CLK_0>,
+				 <&lvds1_i2c0_lpcg IMX_LPCG_CLK_4>;
+			clock-names = "per", "ipg";
+			assigned-clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>;
+			assigned-clock-rates = <24000000>;
+			power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
+			status = "disabled";
+		};
+
+		i2c1_lvds1: i2c@57247000 {
+			compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+			reg = <0x57247000 0x1000>;
+			interrupts = <9>;
+			clocks = <&lvds1_i2c0_lpcg IMX_LPCG_CLK_0>,
+				 <&lvds1_i2c0_lpcg IMX_LPCG_CLK_4>;
+			clock-names = "per", "ipg";
+			assigned-clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>;
+			assigned-clock-rates = <24000000>;
+			power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
index 61986e0639e53..9f29fe4589668 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
@@ -576,3 +576,4 @@  clk_spdif1_rx: clock-spdif1-rx {
 #include "imx8qm-ss-conn.dtsi"
 #include "imx8qm-ss-lsio.dtsi"
 #include "imx8qm-ss-audio.dtsi"
+#include "imx8qm-ss-lvds.dtsi"