From patchwork Thu Jun 6 13:36:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Fancellu X-Patchwork-Id: 13688517 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9BA2EC27C54 for ; Thu, 6 Jun 2024 13:37:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Yb7Ys4CjObM48K7PgalQmGiWoBNB6bUMDA38N9Ja7V4=; b=BmY3Z1K1jb8bgR jOzt0WsyPLCIwJnhIJolnC7ZiKJxpfE46Fjcok895M65yojItq7JND7dzBXu86BXxmSnVkNwZ8XQ+ 5C8QoH4TKdSq0/fqQ9hssnMTco59NvbMuJ3sC7ls1/1cxpRpngQUx5SAvHnbCYrVtKNaTW4usIOa6 e+/vP0mguFvUGbsfT/MdoRd4f01Yrjyv2aovyPJwBTaXE7zo72F5WV4GYNXzVHUNZ647wYLeE1sN4 WYEI7NytuwPGfKVuLUlpeG2ZsZzK5+r0xzY9M3N/lsTa1jkX4DWmo9XGntfBqr5mx2KhGCNYHj+Me uyUcz6oCshmUqTAhiYGg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sFDIR-00000009vZB-28Ni; Thu, 06 Jun 2024 13:36:51 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sFDIK-00000009vTM-1qWU for linux-arm-kernel@lists.infradead.org; Thu, 06 Jun 2024 13:36:46 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 605E71576; Thu, 6 Jun 2024 06:37:06 -0700 (PDT) Received: from e125770.cambridge.arm.com (e125770.arm.com [10.1.199.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 904C63F792; Thu, 6 Jun 2024 06:36:41 -0700 (PDT) From: Luca Fancellu To: linux-arm-kernel@lists.infradead.org Cc: diego.sueiro@arm.com Subject: [boot-wrapper 4/7] gic-v3: Prepare for gicv3 with EL2 Date: Thu, 6 Jun 2024 14:36:25 +0100 Message-Id: <20240606133628.3330423-5-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240606133628.3330423-1-luca.fancellu@arm.com> References: <20240606133628.3330423-1-luca.fancellu@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240606_063644_596295_AAE31050 X-CRM114-Status: GOOD ( 11.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This is a preparation for allowing boot-wrapper configuring the gicv3 with EL2. When supporting boot at EL2 for Armv8-R, the architecture does not define ICC_CTLR_EL2. See [https://developer.arm.com/documentation/ihi0069/latest/]. As the caller, gic_secure_init expects the ICC_CTLR to be written, we change the function into gic_init_icc_ctlr(). In the GIC spec, the r/w bits in this register ([6:0]) either affect EL3 IRQ routing (not applicable since no EL3), non-secure IRQ handling (not applicable since only secure state in Armv8-R aarch64), or are aliased to ICC_CTLR_EL1 bits. So, based on this, the new gic_init_icc_ctlr() would be: When currentEL is EL3, init ICC_CTLR_EL3 as before. When currentEL is not EL3, init ICC_CTLR_EL1 with ICC_CTLR_EL1_RESET. Signed-off-by: Luca Fancellu Reviewed-by: Andre Przywara --- arch/aarch32/include/asm/gic-v3.h | 7 +++++++ arch/aarch64/include/asm/gic-v3.h | 20 +++++++++++++++++--- common/gic-v3.c | 2 +- 3 files changed, 25 insertions(+), 4 deletions(-) diff --git a/arch/aarch32/include/asm/gic-v3.h b/arch/aarch32/include/asm/gic-v3.h index b28136af7fe1..fdfbef859517 100644 --- a/arch/aarch32/include/asm/gic-v3.h +++ b/arch/aarch32/include/asm/gic-v3.h @@ -11,6 +11,8 @@ #include +#define ICC_CTLR_RESET (0UL) + static inline void gic_write_icc_sre(uint32_t val) { mcr(ICC_SRE, val); @@ -21,4 +23,9 @@ static inline void gic_write_icc_ctlr(uint32_t val) mcr(ICC_CTLR, val); } +static inline void gic_init_icc_ctlr() +{ + gic_write_icc_ctlr(ICC_CTLR_RESET); +} + #endif diff --git a/arch/aarch64/include/asm/gic-v3.h b/arch/aarch64/include/asm/gic-v3.h index 24474807c6fe..aca7ab140ed5 100644 --- a/arch/aarch64/include/asm/gic-v3.h +++ b/arch/aarch64/include/asm/gic-v3.h @@ -11,14 +11,28 @@ #include +#define ICC_CTLR_EL3_RESET (0UL) +#define ICC_CTLR_EL1_RESET (0UL) + +static inline uint32_t current_el(void) +{ + return mrs(CurrentEL); +} + static inline void gic_write_icc_sre(uint32_t val) { - msr(ICC_SRE_EL3, val); + if (current_el() == CURRENTEL_EL3) + msr(ICC_SRE_EL3, val); + else + msr(ICC_SRE_EL2, val); } -static inline void gic_write_icc_ctlr(uint32_t val) +static inline void gic_init_icc_ctlr() { - msr(ICC_CTLR_EL3, val); + if (current_el() == CURRENTEL_EL3) + msr(ICC_CTLR_EL3, ICC_CTLR_EL3_RESET); + else + msr(ICC_CTLR_EL1, ICC_CTLR_EL1_RESET); } #endif diff --git a/common/gic-v3.c b/common/gic-v3.c index 6207007959bd..a0fe5642257e 100644 --- a/common/gic-v3.c +++ b/common/gic-v3.c @@ -117,6 +117,6 @@ void gic_secure_init(void) gic_write_icc_sre(ICC_SRE_Enable | ICC_SRE_DIB | ICC_SRE_DFB | ICC_SRE_SRE); isb(); - gic_write_icc_ctlr(0); + gic_init_icc_ctlr(); isb(); }