From patchwork Fri Jun 7 20:31:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 13690650 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0B58EC27C53 for ; Fri, 7 Jun 2024 20:32:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=bddaaTU5ma30xdl0KfYlr8zOXj3LExOMbmQzAJefWhY=; b=BikY1tc0EX2bp/ CU60j1n2hTvGEbpDgwDFgVcbFveryFMiHmL6BdJKXkJzfgYckAYX00RhKJ5upfwNBLrwjGv27pqYT zFq3v+gztb29RApTexNUdNiuQErJJzbOviuc65bfpwwMTdiPJYZhGatfDa3KXXrgQ6pOSxDp8KBoD xQOhFhBa24zLYWP9H/Br4xm1WJtYvHDQ457R3QvVhGOJHbIbHvxMIaHnQ/y4LFWijkMpzhk/+YSUt UNAmD2mphHAr5N+LtOSVIPkRw4qBdFBVcIbHWldqJG29YAa/vJ5Uc/247xZG9Xk1OJolKVrQWTdrq zO0JyunA+UNRQJCv6rCQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sFgGI-0000000FaMP-43P7; Fri, 07 Jun 2024 20:32:35 +0000 Received: from sin.source.kernel.org ([2604:1380:40e1:4800::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sFgFy-0000000Fa5K-46ZW for linux-arm-kernel@lists.infradead.org; Fri, 07 Jun 2024 20:32:20 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id 318BBCE1E87; Fri, 7 Jun 2024 20:32:13 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A82C7C32782; Fri, 7 Jun 2024 20:32:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1717792332; bh=0PuD070n2iQEaU9GwC/6rdl3ex4y0laQrCuOVZ80ZSM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=KAUj+VV4IljDqnnGXjXbzgTEJO9m2AWbY51T7niBiiXSJgW/4fkvZJuCOlqAw4X5G b+f5H1ZTXo9khnQEN7o/eSXMOUA7gVZtvCZ/xmPtpEnA3BYSrnh78upORearDd8rJ2 zzbzGpkbKLjh439z3pcJ1EI1BsWCl3Zpu9kw17GAC4P8A8husFUQk7yjjuK7ZKwLpS VJP2+OKt1hEUsUkUsTO10AJKd9vIkV3RDFO5bLiIt9Q3GF9YirLGQPxoqGX/8pU0vB RyFilF/uBjTzHtMYtvDNR5DNB3v6vNUq6mb3ItKcsqBTBRdxmMBaoFjh3hLzKfNOK3 W+ksPlXAkBgZw== From: "Rob Herring (Arm)" Date: Fri, 07 Jun 2024 14:31:32 -0600 Subject: [PATCH 7/9] arm64: perf/kvm: Use a common PMU cycle counter define MIME-Version: 1.0 Message-Id: <20240607-arm-pmu-3-9-icntr-v1-7-c7bd2dceff3b@kernel.org> References: <20240607-arm-pmu-3-9-icntr-v1-0-c7bd2dceff3b@kernel.org> In-Reply-To: <20240607-arm-pmu-3-9-icntr-v1-0-c7bd2dceff3b@kernel.org> To: Russell King , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , Catalin Marinas Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, kvmarm@lists.linux.dev X-Mailer: b4 0.14-dev X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240607_133215_431085_2894B5B0 X-CRM114-Status: GOOD ( 17.69 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The PMUv3 and KVM code each have a define for the PMU cycle counter index. Move KVM's define to a shared location and use it for PMUv3 driver. Signed-off-by: Rob Herring (Arm) --- arch/arm/include/asm/arm_pmuv3.h | 2 ++ arch/arm64/include/asm/arm_pmuv3.h | 2 ++ arch/arm64/kvm/sys_regs.c | 1 + drivers/perf/arm_pmuv3.c | 23 +++++++++-------------- include/kvm/arm_pmu.h | 1 - 5 files changed, 14 insertions(+), 15 deletions(-) diff --git a/arch/arm/include/asm/arm_pmuv3.h b/arch/arm/include/asm/arm_pmuv3.h index a41b503b7dcd..ac2cf37b57e3 100644 --- a/arch/arm/include/asm/arm_pmuv3.h +++ b/arch/arm/include/asm/arm_pmuv3.h @@ -9,6 +9,8 @@ #include #include +#define ARMV8_PMU_CYCLE_IDX 31 + #define PMCCNTR __ACCESS_CP15_64(0, c9) #define PMCR __ACCESS_CP15(c9, 0, c12, 0) diff --git a/arch/arm64/include/asm/arm_pmuv3.h b/arch/arm64/include/asm/arm_pmuv3.h index 1ed91334fede..46930729fb3f 100644 --- a/arch/arm64/include/asm/arm_pmuv3.h +++ b/arch/arm64/include/asm/arm_pmuv3.h @@ -11,6 +11,8 @@ #include #include +#define ARMV8_PMU_CYCLE_IDX 31 + #define RETURN_READ_PMEVCNTRN(n) \ return read_sysreg(pmevcntr##n##_el0) static inline unsigned long read_pmevcntrn(int n) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index f8b5db48ea8a..22393ae7ce14 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -18,6 +18,7 @@ #include #include +#include #include #include #include diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c index 3b49144f3a58..468a0a3bbd5a 100644 --- a/drivers/perf/arm_pmuv3.c +++ b/drivers/perf/arm_pmuv3.c @@ -448,11 +448,6 @@ static const struct attribute_group armv8_pmuv3_caps_attr_group = { .attrs = armv8_pmuv3_caps_attrs, }; -/* - * Perf Events' indices - */ -#define ARMV8_IDX_CYCLE_COUNTER 31 - /* * We unconditionally enable ARMv8.5-PMU long event counter support * (64-bit events) where supported. Indicate if this arm_pmu has long @@ -484,7 +479,7 @@ static bool armv8pmu_event_is_chained(struct perf_event *event) return !armv8pmu_event_has_user_read(event) && armv8pmu_event_is_64bit(event) && !armv8pmu_has_long_event(cpu_pmu) && - (idx != ARMV8_IDX_CYCLE_COUNTER); + (idx != ARMV8_PMU_CYCLE_IDX); } /* @@ -543,7 +538,7 @@ static bool armv8pmu_event_needs_bias(struct perf_event *event) return false; if (armv8pmu_has_long_event(cpu_pmu) || - idx == ARMV8_IDX_CYCLE_COUNTER) + idx == ARMV8_PMU_CYCLE_IDX) return true; return false; @@ -571,7 +566,7 @@ static u64 armv8pmu_read_counter(struct perf_event *event) int idx = hwc->idx; u64 value; - if (idx == ARMV8_IDX_CYCLE_COUNTER) + if (idx == ARMV8_PMU_CYCLE_IDX) value = read_pmccntr(); else value = armv8pmu_read_hw_counter(event); @@ -604,7 +599,7 @@ static void armv8pmu_write_counter(struct perf_event *event, u64 value) value = armv8pmu_bias_long_counter(event, value); - if (idx == ARMV8_IDX_CYCLE_COUNTER) + if (idx == ARMV8_PMU_CYCLE_IDX) write_pmccntr(value); else armv8pmu_write_hw_counter(event, value); @@ -641,7 +636,7 @@ static void armv8pmu_write_event_type(struct perf_event *event) armv8pmu_write_evtype(idx - 1, hwc->config_base); armv8pmu_write_evtype(idx, chain_evt); } else { - if (idx == ARMV8_IDX_CYCLE_COUNTER) + if (idx == ARMV8_PMU_CYCLE_IDX) write_pmccfiltr(hwc->config_base); else armv8pmu_write_evtype(idx, hwc->config_base); @@ -768,7 +763,7 @@ static void armv8pmu_enable_user_access(struct arm_pmu *cpu_pmu) /* Clear any unused counters to avoid leaking their contents */ for_each_clear_bit(i, cpuc->used_mask, ARMPMU_MAX_HWEVENTS) { - if (i == ARMV8_IDX_CYCLE_COUNTER) + if (i == ARMV8_PMU_CYCLE_IDX) write_pmccntr(0); else armv8pmu_write_evcntr(i, 0); @@ -928,8 +923,8 @@ static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc, /* Always prefer to place a cycle counter into the cycle counter. */ if (evtype == ARMV8_PMUV3_PERFCTR_CPU_CYCLES) { - if (!test_and_set_bit(ARMV8_IDX_CYCLE_COUNTER, cpuc->used_mask)) - return ARMV8_IDX_CYCLE_COUNTER; + if (!test_and_set_bit(ARMV8_PMU_CYCLE_IDX, cpuc->used_mask)) + return ARMV8_PMU_CYCLE_IDX; else if (armv8pmu_event_is_64bit(event) && armv8pmu_event_want_user_access(event) && !armv8pmu_has_long_event(cpu_pmu)) @@ -1191,7 +1186,7 @@ static void __armv8pmu_probe_pmu(void *info) 0, FIELD_GET(ARMV8_PMU_PMCR_N, armv8pmu_pmcr_read())); /* Add the CPU cycles counter */ - bitmap_set(cpu_pmu->cntr_mask, ARMV8_IDX_CYCLE_COUNTER, 1); + bitmap_set(cpu_pmu->cntr_mask, ARMV8_PMU_CYCLE_IDX, 1); pmceid[0] = pmceid_raw[0] = read_pmceid0(); pmceid[1] = pmceid_raw[1] = read_pmceid1(); diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h index 334d7c5503cf..871067fb2616 100644 --- a/include/kvm/arm_pmu.h +++ b/include/kvm/arm_pmu.h @@ -10,7 +10,6 @@ #include #include -#define ARMV8_PMU_CYCLE_IDX (ARMV8_PMU_MAX_COUNTERS - 1) #if IS_ENABLED(CONFIG_HW_PERF_EVENTS) && IS_ENABLED(CONFIG_KVM) struct kvm_pmc {