From patchwork Tue Jun 11 15:50:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 13693952 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A9FC3C27C75 for ; Tue, 11 Jun 2024 15:51:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=itFKyZeBhzC81auZNCwnyH04HPRGuHc3sSWKRLdjD0g=; b=SS63/LzLuv4SfA aGN+vL2OcOeV8Bk5SqUQWnoVwY2Z4wWZBnPBHSjCRVrtgNaJezg+lKKClwkXOL5Gu/9v9/oHG2SMJ jWrQS+v57ROVyJDUFEADBldGeO2VnraF1znQ3/3XDrTKz3FnWdRS1h/s2Pz5C1zDRSmCZrLYKihpS QzVNjspE0OYkYg6hEcNZpoCaGmXLSw34KmeQqisYdv4641AB5no4I+huOI1seScSosNJWps6Pl0D/ /egQsBbwIENVGFF4e8flPC+ED72g09Q1F8f7J6GoWJy0K3ISib3Nnpf/BXKaEU4k+qAylNhwmkupt nBF02BilnfJgPvUiuKXg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sH3lo-00000009OVW-3Eoa; Tue, 11 Jun 2024 15:50:48 +0000 Received: from sin.source.kernel.org ([2604:1380:40e1:4800::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sH3lm-00000009OUl-1MQi for linux-arm-kernel@lists.infradead.org; Tue, 11 Jun 2024 15:50:47 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id 61B9ECE1C44; Tue, 11 Jun 2024 15:50:44 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 54342C2BD10; Tue, 11 Jun 2024 15:50:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718121043; bh=jI5NwtYOV0N7nO4N65St6X+X54gw21IY5Jfh68MvKFc=; h=From:To:Cc:Subject:Date:From; b=cYrmGG+VOiG6F1oIC4PjKOeTRoG9mBdxYDYssNT0OBR+iPB3Rc1sm7gawmmu/GyZv LNTZ+61jUVnWtOsWn0T+JcOEniZNnyqLai4LqJvZCzskRl6i1adksxDE0R2fnyg1Ts hIcjD7tX9KIWQYng1N6aXsj3Szci5/yifH/yZThbSULOMaR7G5W76lnVK6jTjPVy5a wgqzGZdldEIDM4PMCmhtx6YM4KGRLV8+POTyz7HbiVhsXW/mkT6CeM6mBlrDFBASLo uzBQj2TDAZOQfHOZiOxwD3ZrErTlTtsym6V4nkec9KR4t+pc+T58VqmF8cmWQDaGly vvOMH7R9oD51g== From: "Rob Herring (Arm)" To: Will Deacon , Mark Rutland , James Clark Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] perf: arm_pmuv3: Avoid assigning fixed cycle counter with threshold Date: Tue, 11 Jun 2024 09:50:12 -0600 Message-ID: <20240611155012.2286044-1-robh@kernel.org> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240611_085046_564592_5779AB9A X-CRM114-Status: GOOD ( 12.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org If the user has requested a counting threshold for the CPU cycles event, then the fixed cycle counter can't be assigned as it lacks threshold support. Currently, the thresholds will work or not randomly depending on which counter the event is assigned. While using thresholds for CPU cycles doesn't make much sense, it can be useful for testing purposes. Fixes: 816c26754447 ("arm64: perf: Add support for event counting threshold") Signed-off-by: Rob Herring (Arm) --- drivers/perf/arm_pmuv3.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c index 23fa6c5da82c..2612be29ee23 100644 --- a/drivers/perf/arm_pmuv3.c +++ b/drivers/perf/arm_pmuv3.c @@ -939,9 +939,10 @@ static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc, struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); struct hw_perf_event *hwc = &event->hw; unsigned long evtype = hwc->config_base & ARMV8_PMU_EVTYPE_EVENT; + bool has_threshold = !!(hwc->config_base & ARMV8_PMU_EVTYPE_TH); /* Always prefer to place a cycle counter into the cycle counter. */ - if (evtype == ARMV8_PMUV3_PERFCTR_CPU_CYCLES) { + if ((evtype == ARMV8_PMUV3_PERFCTR_CPU_CYCLES) && !has_threshold) { if (!test_and_set_bit(ARMV8_IDX_CYCLE_COUNTER, cpuc->used_mask)) return ARMV8_IDX_CYCLE_COUNTER; else if (armv8pmu_event_is_64bit(event) &&