From patchwork Wed Jun 12 13:24:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siddharth Vadapalli X-Patchwork-Id: 13694999 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 967F7C27C7B for ; Wed, 12 Jun 2024 13:24:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=fLaRYpszCyI+VJCixfWCXgonJjYfNx/QeL5FWpsKpEw=; b=zmS3yJv4zHFdi3vNZFAomK68EZ Hv9hhk+mKDIM0dDcoAnKy1yW3Lz169aF+0dmey86uD9qw7tJSiiL/6hbA/VD3nK7vbeY+bHtTUkXy wjI4fFqak77pvJYVLlH70D0nOUbB307LBzUzihkJprl0U6fVqGt9EASrxQ79bch7J8/Ft83UcsRDl +ug6QS9U4OdYpzq/Ae13MLhUPZAiIiAHIdj9METpHkeb7wnFQxwbVIN2mPr4FSujIcR6nhSQ6ERvn k51gdYSMlKFydrdbxBXSJFDI6chHN9stEWMGcvVOI5ST6pNMsqWmY0IGHzbtIb8uAoR5wKlhnTBZE qyq+mHUA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sHNxx-0000000Cj39-42Uo; Wed, 12 Jun 2024 13:24:41 +0000 Received: from fllv0015.ext.ti.com ([198.47.19.141]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sHNxr-0000000CiyA-49Xr for linux-arm-kernel@lists.infradead.org; Wed, 12 Jun 2024 13:24:37 +0000 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 45CDOXfB115286; Wed, 12 Jun 2024 08:24:33 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1718198673; bh=fLaRYpszCyI+VJCixfWCXgonJjYfNx/QeL5FWpsKpEw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=PCEVruWUDvPA6pzAIJUkJ70HqzHsuO7eD3qYp4vTHJf+h07PBJlKVpCCvFEwqjUAQ E2itxdfeoJL8FIngqV+q7PbSM4qAwa+msguPkch3nGZXtyO+Pm6mPMoCcUFq+9PhON 7ZtWlP5oHSx3o7/nkCZpuILPB8C4VSgEE1RF1p2k= Received: from DLEE106.ent.ti.com (dlee106.ent.ti.com [157.170.170.36]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 45CDOXBj004775 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 12 Jun 2024 08:24:33 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 12 Jun 2024 08:24:32 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 12 Jun 2024 08:24:32 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 45CDOAmu046478; Wed, 12 Jun 2024 08:24:28 -0500 From: Siddharth Vadapalli To: , , , , , , , CC: , , , , , , Subject: [PATCH v6 4/8] arm64: dts: ti: k3-j722s: Switch to k3-am62p-j722s-common-{}.dtsi includes Date: Wed, 12 Jun 2024 18:54:05 +0530 Message-ID: <20240612132409.2477888-5-s-vadapalli@ti.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240612132409.2477888-1-s-vadapalli@ti.com> References: <20240612132409.2477888-1-s-vadapalli@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240612_062436_267002_03C42655 X-CRM114-Status: GOOD ( 13.97 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Update "k3-j722s.dtsi" to include "k3-am62p-j722s-common-{}".dtsi files in order to reuse the nodes shared with AM62P. Also include the J722S specific "k3-j722s-main.dtsi". Since the J7 family of SoCs has the k3-{soc}.dtsi file organized as: k3-{soc}.dtsi = CPU + Cache + CBASS-Ranges + "Peripheral-Includes" switch the "k3-j722s.dtsi" file to the same convention. Signed-off-by: Siddharth Vadapalli Acked-by: Roger Quadros --- v5: https://lore.kernel.org/r/20240604085252.3686037-5-s-vadapalli@ti.com/ Changes since v5: - Rather than including "k3-am62p-j722s-common.dtsi" which is the equivalent of "k3-am62p.dtsi" in the current series, k3-j722s.dtsi includes "k3-am62p-j722s-common-{}.dtsi" and "k3-j722s-main.dtsi". Also, to match the J7 family of SoCs, the CPU, Cache and CBASS-Ranges are included in "k3-j722s.dtsi". arch/arm64/boot/dts/ti/k3-j722s.dtsi | 158 ++++++++++++++++++++++++++- 1 file changed, 157 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi index c75744edb143..1bcbc9152ff0 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi @@ -10,11 +10,133 @@ #include #include -#include "k3-am62p5.dtsi" +#include "k3-pinctrl.h" / { model = "Texas Instruments K3 J722S SoC"; compatible = "ti,j722s"; + interrupt-parent = <&gic500>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0: cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + reg = <0x000>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + clocks = <&k3_clks 135 0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53"; + reg = <0x001>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + clocks = <&k3_clks 136 0>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a53"; + reg = <0x002>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + clocks = <&k3_clks 137 0>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a53"; + reg = <0x003>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + clocks = <&k3_clks 138 0>; + }; + }; + + l2_0: l2-cache0 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + psci: psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + }; + + a53_timer0: timer-cl0-cpu0 { + compatible = "arm,armv8-timer"; + interrupts = , /* cntpsirq */ + , /* cntpnsirq */ + , /* cntvirq */ + ; /* cnthpirq */ + }; + + pmu: pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; cbass_main: bus@f0000 { compatible = "simple-bus"; @@ -74,9 +196,43 @@ cbass_main: bus@f0000 { <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; + + cbass_mcu: bus@4000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, /* Peripheral window */ + <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */ + <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */ + <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU IRAM0 */ + <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>; /* MCU IRAM1 */ + bootph-all; + }; + + cbass_wakeup: bus@b00000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ + <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */ + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* WKUP CTRL MMR */ + <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/ + <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/ + bootph-all; + }; }; + + #include "k3-am62p-j722s-common-thermal.dtsi" }; +/* Include peripherals shared with AM62P */ +#include "k3-am62p-j722s-common-main.dtsi" +#include "k3-am62p-j722s-common-mcu.dtsi" +#include "k3-am62p-j722s-common-wakeup.dtsi" + +/* Include J722S specific peripherals */ +#include "k3-j722s-main.dtsi" + /* Main domain overrides */ &inta_main_dmss {