From patchwork Wed Jun 12 13:24:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siddharth Vadapalli X-Patchwork-Id: 13695001 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3E7D5C27C7B for ; Wed, 12 Jun 2024 13:25:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=4isp7/3bMlnEnXlgtEaJaWiCfyzYElSDJiQ9Orlzc/M=; b=XQW2iSOjsiyfMVYcHbBakC7umq qiZKAjKv7JrrH24EgMV4n1zrlDmlW3D5novbYnEb8qJBeqFQcr6xmNSpgKxvQBshnRmqIZ/laE4JN E/Rj5peD05Wcm1Mnux+Md4PFSnZYhw4fQJ4Tkh2p3QU8MktqkoViQkv1GIrVJlzhGBwgWg44mDr36 Q2x1Oq4P1PEIvgDhml2NCYAwiHe1H5/GBGUhjFnXl1NdrhBbEKXxMMulcSZineH6XQs5IgExq2DNM 7mI+q+ohNI80eH2rVwlw1i8Ysyh0hRtbnxw823f8E7huPjQB7PLJTYke0mYQuquuf7Cqg4epucP7f ieDQ7tBA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sHNyE-0000000CjF0-2KcK; Wed, 12 Jun 2024 13:24:58 +0000 Received: from fllv0016.ext.ti.com ([198.47.19.142]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sHNy0-0000000Cj4Y-0k9y for linux-arm-kernel@lists.infradead.org; Wed, 12 Jun 2024 13:24:46 +0000 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 45CDOfpF079277; Wed, 12 Jun 2024 08:24:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1718198681; bh=4isp7/3bMlnEnXlgtEaJaWiCfyzYElSDJiQ9Orlzc/M=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=sm7zEfkD4HmXOnTayhTjrfB54IoJjWG3DM+v2fPvS+58Dmz0RvRmdWVAFsgkB9lUo cyLT2850SV1L+2C0sMcKL7Q4Nfzwjr4oMNkvKrwUH2ibXkxZNz3Xcqg68v7M9aY2L4 I9spoQoZtWKVx5dhvy8Alewp+I/T6SrzlIpgaPkg= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 45CDOf1O065614 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 12 Jun 2024 08:24:41 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 12 Jun 2024 08:24:41 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 12 Jun 2024 08:24:41 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 45CDOAmw046478; Wed, 12 Jun 2024 08:24:37 -0500 From: Siddharth Vadapalli To: , , , , , , , CC: , , , , , , Subject: [PATCH v6 6/8] arm64: dts: ti: k3-serdes: Add SERDES0/SERDES1 lane-muxing macros for J722S Date: Wed, 12 Jun 2024 18:54:07 +0530 Message-ID: <20240612132409.2477888-7-s-vadapalli@ti.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240612132409.2477888-1-s-vadapalli@ti.com> References: <20240612132409.2477888-1-s-vadapalli@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240612_062444_535404_20F7BDCB X-CRM114-Status: GOOD ( 10.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The SERDES0 and SERDES1 instances of SERDES on J722S are single lane SERDES which are individually muxed across different peripherals. LANE0 of SERDES0 is muxed between USB and CPSW while LANE0 of SERDES1 is muxed between PCIe and CPSW. Define the lane-muxing macros to be used as the idle state values. Co-developed-by: Ravi Gunasekaran Signed-off-by: Ravi Gunasekaran Signed-off-by: Siddharth Vadapalli Reviewed-by: Roger Quadros --- v5: https://lore.kernel.org/r/20240604085252.3686037-6-s-vadapalli@ti.com/ Changes since v5: - Collected Reviewed-by tag from Roger Quadros arch/arm64/boot/dts/ti/k3-serdes.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-serdes.h b/arch/arm64/boot/dts/ti/k3-serdes.h index a011ad893b44..ef3606068140 100644 --- a/arch/arm64/boot/dts/ti/k3-serdes.h +++ b/arch/arm64/boot/dts/ti/k3-serdes.h @@ -201,4 +201,12 @@ #define J784S4_SERDES4_LANE3_USB 0x2 #define J784S4_SERDES4_LANE3_IP4_UNUSED 0x3 +/* J722S */ + +#define J722S_SERDES0_LANE0_USB 0x0 +#define J722S_SERDES0_LANE0_QSGMII_LANE2 0x1 + +#define J722S_SERDES1_LANE0_PCIE0_LANE0 0x0 +#define J722S_SERDES1_LANE0_QSGMII_LANE1 0x1 + #endif /* DTS_ARM64_TI_K3_SERDES_H */