From patchwork Thu Jun 13 09:45:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anshuman Khandual X-Patchwork-Id: 13696545 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 37BEBC27C4F for ; Thu, 13 Jun 2024 09:46:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=In0Zougz0wW3A2K9wsMBDeY7vG73Mat4r/0Mrhi7UqE=; b=ROt0WXpKkh/qeBBC2uXlZAV+0S b9KJNNkjQ66pIxhX7jU/ot7Weboyri2qmsJ2KLBTVDDkTUSmy+x/h0HUB6hRRXYnh4lbYXKeQVdbZ RJAY7VRj9/SOR7cY6EVT3oPrJj+ooWDfy/tYIqyENCTGp8oG8EnALXGjZdLPJRkkq5tvniAB37+C9 GrAKq12HoQCSy0liq8BSD0uHjyVy3aTlI8ShwRktKwotM7Lb6vRSCC5nCMAC/zE7XgHLitAGkvWLf IvixK5a72vMxxfa4034BLGADIH1X0Iqz6JD0BySmezU+g8Dn46vkxF66JFHiSZDUq6OC8vRpS5tAk 6UdTHMzQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sHh1l-0000000G1bW-0bf2; Thu, 13 Jun 2024 09:45:53 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sHh1i-0000000G1ap-1m1f for linux-arm-kernel@lists.infradead.org; Thu, 13 Jun 2024 09:45:52 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F2AD61063; Thu, 13 Jun 2024 02:46:13 -0700 (PDT) Received: from a077893.arm.com (unknown [10.163.44.128]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 871943F5A1; Thu, 13 Jun 2024 02:45:46 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: mark.rutland@arm.com, ryan.roberts@arm.com, Anshuman Khandual , Catalin Marinas , Will Deacon , Marc Zyngier , linux-kernel@vger.kernel.org Subject: [PATCH] arm64/mm: Drop ESR_ELx_FSC_TYPE Date: Thu, 13 Jun 2024 15:15:38 +0530 Message-Id: <20240613094538.3263536-1-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240613_024550_587109_D019AAB8 X-CRM114-Status: GOOD ( 12.36 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Fault status codes at page table level 0, 1, 2 and 3 for access, permission and translation faults are architecturally organized in a way, that masking out ESR_ELx_FSC_TYPE, fetches Level 0 status code for the respective fault. Helpers like esr_fsc_is_[translation|permission|access_flag]_fault() mask out ESR_ELx_FSC_TYPE before comparing against corresponding Level 0 status code as the kernel does not yet care about the page table level, the fault really occurred previously. This scheme is starting to crumble after FEAT_LPA2 when level -1 got added. Fault status code for translation fault at level -1 is 0x2B which does not follow ESR_ELx_FSC_TYPE, requiring esr_fsc_is_translation_fault() changes. This changes above helpers to compare against individual fault status code values for each page table level and drop ESR_ELx_FSC_TYPE which is losing its value as a common mask. Cc: Catalin Marinas Cc: Will Deacon Cc: Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual Reviewed-by: Ryan Roberts Acked-by: Mark Rutland --- This applies on 6.10-rc3 arch/arm64/include/asm/esr.h | 42 +++++++++++++++++++++++++++--------- arch/arm64/mm/fault.c | 4 ++-- 2 files changed, 34 insertions(+), 12 deletions(-) diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h index 7abf09df7033..8cc0311d3fba 100644 --- a/arch/arm64/include/asm/esr.h +++ b/arch/arm64/include/asm/esr.h @@ -109,14 +109,23 @@ /* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */ #define ESR_ELx_FSC (0x3F) -#define ESR_ELx_FSC_TYPE (0x3C) #define ESR_ELx_FSC_LEVEL (0x03) #define ESR_ELx_FSC_EXTABT (0x10) #define ESR_ELx_FSC_MTE (0x11) #define ESR_ELx_FSC_SERROR (0x11) -#define ESR_ELx_FSC_ACCESS (0x08) -#define ESR_ELx_FSC_FAULT (0x04) -#define ESR_ELx_FSC_PERM (0x0C) +#define ESR_ELx_FSC_ACCESS_L0 (0x08) +#define ESR_ELx_FSC_ACCESS_L1 (0x09) +#define ESR_ELx_FSC_ACCESS_L2 (0x0A) +#define ESR_ELx_FSC_ACCESS_L3 (0x0B) +#define ESR_ELx_FSC_FAULT_LN1 (0x2B) +#define ESR_ELx_FSC_FAULT_L0 (0x04) +#define ESR_ELx_FSC_FAULT_L1 (0x05) +#define ESR_ELx_FSC_FAULT_L2 (0x06) +#define ESR_ELx_FSC_FAULT_L3 (0x07) +#define ESR_ELx_FSC_PERM_L0 (0x0C) +#define ESR_ELx_FSC_PERM_L1 (0x0D) +#define ESR_ELx_FSC_PERM_L2 (0x0E) +#define ESR_ELx_FSC_PERM_L3 (0x0F) #define ESR_ELx_FSC_SEA_TTW(n) (0x14 + (n)) #define ESR_ELx_FSC_SECC (0x18) #define ESR_ELx_FSC_SECC_TTW(n) (0x1c + (n)) @@ -388,20 +397,33 @@ static inline bool esr_is_data_abort(unsigned long esr) static inline bool esr_fsc_is_translation_fault(unsigned long esr) { - /* Translation fault, level -1 */ - if ((esr & ESR_ELx_FSC) == 0b101011) - return true; - return (esr & ESR_ELx_FSC_TYPE) == ESR_ELx_FSC_FAULT; + esr = esr & ESR_ELx_FSC; + + return (esr == ESR_ELx_FSC_FAULT_L3) || + (esr == ESR_ELx_FSC_FAULT_L2) || + (esr == ESR_ELx_FSC_FAULT_L1) || + (esr == ESR_ELx_FSC_FAULT_L0) || + (esr == ESR_ELx_FSC_FAULT_LN1); } static inline bool esr_fsc_is_permission_fault(unsigned long esr) { - return (esr & ESR_ELx_FSC_TYPE) == ESR_ELx_FSC_PERM; + esr = esr & ESR_ELx_FSC; + + return (esr == ESR_ELx_FSC_PERM_L3) || + (esr == ESR_ELx_FSC_PERM_L2) || + (esr == ESR_ELx_FSC_PERM_L1) || + (esr == ESR_ELx_FSC_PERM_L0); } static inline bool esr_fsc_is_access_flag_fault(unsigned long esr) { - return (esr & ESR_ELx_FSC_TYPE) == ESR_ELx_FSC_ACCESS; + esr = esr & ESR_ELx_FSC; + + return (esr == ESR_ELx_FSC_ACCESS_L3) || + (esr == ESR_ELx_FSC_ACCESS_L2) || + (esr == ESR_ELx_FSC_ACCESS_L1) || + (esr == ESR_ELx_FSC_ACCESS_L0); } /* Indicate whether ESR.EC==0x1A is for an ERETAx instruction */ diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c index 451ba7cbd5ad..7199aaff2a29 100644 --- a/arch/arm64/mm/fault.c +++ b/arch/arm64/mm/fault.c @@ -440,7 +440,7 @@ static void set_thread_esr(unsigned long address, unsigned long esr) */ esr &= ESR_ELx_EC_MASK | ESR_ELx_IL | ESR_ELx_CM | ESR_ELx_WNR; - esr |= ESR_ELx_FSC_FAULT; + esr |= ESR_ELx_FSC_FAULT_L0; break; case ESR_ELx_EC_IABT_LOW: /* @@ -449,7 +449,7 @@ static void set_thread_esr(unsigned long address, unsigned long esr) * reported with that DFSC value, so we clear them. */ esr &= ESR_ELx_EC_MASK | ESR_ELx_IL; - esr |= ESR_ELx_FSC_FAULT; + esr |= ESR_ELx_FSC_FAULT_L0; break; default: /*