diff mbox series

[3/4] arm64: dts: imx95-19x19-evk: add lpi2c7 and expander gpio pcal6524

Message ID 20240617223100.1539796-3-Frank.Li@nxp.com (mailing list archive)
State New, archived
Headers show
Series [1/4] arm64: dts: imx95: add '#address-cells' and '#size-cells' for all i2c | expand

Commit Message

Frank Li June 17, 2024, 10:30 p.m. UTC 
Add lpi2c7 and expander gpio pcal6524.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 .../boot/dts/freescale/imx95-19x19-evk.dts    | 34 +++++++++++++++++++
 1 file changed, 34 insertions(+)

Comments

Fabio Estevam June 18, 2024, 2:05 a.m. UTC | #1 
On Mon, Jun 17, 2024 at 7:31 PM Frank Li <Frank.Li@nxp.com> wrote:

> +&lpi2c7 {
> +       clock-frequency = <1000000>;
> +       pinctrl-names = "default", "sleep";
> +       pinctrl-0 = <&pinctrl_lpi2c7>;
> +       pinctrl-1 = <&pinctrl_lpi2c7>;

The default and sleep are the same. Is this intended?
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
index 675abb70aa18d..636907c852e78 100644
--- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
@@ -53,6 +53,27 @@  reg_usdhc2_vmmc: regulator-usdhc2 {
 	};
 };
 
+&lpi2c7 {
+	clock-frequency = <1000000>;
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_lpi2c7>;
+	pinctrl-1 = <&pinctrl_lpi2c7>;
+	status = "okay";
+
+	i2c7_pcal6524: i2c7-gpio@22 {
+		compatible = "nxp,pcal6524";
+		reg = <0x22>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_i2c7_pcal6524>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gpio5>;
+		interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
+
 &lpuart1 {
 	/* console */
 	pinctrl-names = "default";
@@ -95,6 +116,19 @@  &wdog3 {
 };
 
 &scmi_iomuxc {
+	pinctrl_i2c7_pcal6524: i2c7pcal6524grp {
+		fsl,pins = <
+			IMX95_PAD_GPIO_IO36__GPIO5_IO_BIT16			0x31e
+		>;
+	};
+
+	pinctrl_lpi2c7: lpi2c7grp {
+		fsl,pins = <
+			IMX95_PAD_GPIO_IO08__LPI2C7_SDA			0x40000b9e
+			IMX95_PAD_GPIO_IO09__LPI2C7_SCL			0x40000b9e
+		>;
+	};
+
 	pinctrl_uart1: uart1grp {
 		fsl,pins = <
 			IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX      0x31e