From patchwork Tue Jun 18 12:08:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Duje_Mihanovi=C4=87_via_B4_Relay?= X-Patchwork-Id: 13702167 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 069CCC2BB85 for ; Tue, 18 Jun 2024 12:10:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Reply-To:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To: References:Message-Id:Content-Transfer-Encoding:Content-Type:MIME-Version: Subject:Date:From:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=2iY7P0d9jtGx15LOEkKuAOagvBRD/YI04IAWkS+BiC8=; b=ijPi70LH3m2exmK0GsfjHKRPKZ giC5rDqD3Pt8VkLRaVSprGWDQuZDNha7+NIX9TjVkNdAT8pR28W+eXbdCCuqFRu09OjSEEBb2QitT PQMke5qpCZyU2uyW8yvmouK0RCa7ciLyNHwXLnHLU1JmSU5nxDvD8LLm3puBB43rVw/EBuCnp5T7T 0SSz6HJf3tSsBp4V56wn/JpJGz60y2+ux6888szdb8mBSexpIwEfcm+B7OAS/zo/OO7RgreOP41hU i6V9JVUjwTTIrmYXSHdYbPoBiX1EJWm/zzBIQ1ffwvqQOqKArAnWBjaScxk/jk0VN6w2LyNWCe3Op tITXrSyg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sJXfU-0000000EoKh-3XAD; Tue, 18 Jun 2024 12:10:33 +0000 Received: from sin.source.kernel.org ([2604:1380:40e1:4800::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sJXeJ-0000000EndI-40nb for linux-arm-kernel@lists.infradead.org; Tue, 18 Jun 2024 12:09:24 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id E30A0CE1AE6; Tue, 18 Jun 2024 12:09:17 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPS id 303B4C4DDE8; Tue, 18 Jun 2024 12:09:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718712556; bh=HTq8KxdlBff6aHVfaDL9tdZs8oniKPuVqDJdX3FXXA0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=ZfxtaYIBpFo/eSddSB3ZUexCyIph+wbPEJkhdqUTtCN3GHVZojd9BjPxQvGIPIdhs KyESpCRtLsxK0b4X3Jl5rAOuhX//21SOR+CU5soKAIHOc5w9Q3cXcK9MJSO95yL//O YIuD3Rv3T7a3KfyPiiCKokEasvp2J9ehqS+0NtC3dFo987muoj83BYyXRJC2bItrdN Q24EFiyzi70V2DOEv6M+F3ag3/O1jIfvTod7Ql3tJNQvGfVPoVA8G6N+jhs9t8Y9i5 7SnnyXcNkC/2HAeLhnzYWynt08HvNa6zj+RPoTRyrOFWgGz7OqQyK5RWsXfJ7uZY+4 zw6s7AUjF0uwA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21E08C2BB85; Tue, 18 Jun 2024 12:09:16 +0000 (UTC) From: =?utf-8?q?Duje_Mihanovi=C4=87_via_B4_Relay?= Date: Tue, 18 Jun 2024 14:08:15 +0200 Subject: [PATCH RESEND v10 04/12] dt-bindings: clock: Add Marvell PXA1908 clock bindings MIME-Version: 1.0 Message-Id: <20240618-pxa1908-lkml-v10-4-754e5ece9078@skole.hr> References: <20240618-pxa1908-lkml-v10-0-754e5ece9078@skole.hr> In-Reply-To: <20240618-pxa1908-lkml-v10-0-754e5ece9078@skole.hr> To: Michael Turquette , Stephen Boyd , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tony Lindgren , Haojian Zhuang , =?utf-8?q?Duje_Mihanovi=C4=87?= , Lubomir Rintel , Catalin Marinas , Will Deacon , Tony Luck , "Guilherme G. Piccoli" , Rob Herring , Kees Cook Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Karel Balej , David Wronek , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Conor Dooley X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4973; i=duje.mihanovic@skole.hr; h=from:subject:message-id; bh=KMQL466nychebb4YZnaiI07BFVr6kSgzNovpEb0k4I8=; b=owEBbAKT/ZANAwAIAZoRnrBCLZbhAcsmYgBmcXjRRL/KB79VdAD00m7pI+Qx2Y4lftZ7zuNdZ LlQBrgkTxWJAjIEAAEIAB0WIQRT351NnD/hEPs2LXiaEZ6wQi2W4QUCZnF40QAKCRCaEZ6wQi2W 4SluD/dOT8CXrU6hnKj3lUgT0Y0851jToNBWw8imYjNQuQbD9UHGAK8Z1yUhjA/x78ca7WNKyPl 1c7o+pKj7/WdVkjEBXYT76ZN5fU/8aZSDLEoslQoX2B0vBT9l+6UED2enk85gTLaGVKyYb2DL/R 6OMaJVT2/DHbc1slUM6Cx1jKYLjTbFCuVKE/KOhDI3Dvelpy648GDHImwL3Y6bzX0b7mYSa8tE1 /MXHGgXYUryikSxwrEtPHMKz3D5otl/lxsUA+ow2xTie3MOeAeUhTN3x4KwNYQ4MFh/BM9iga4y spW7MbaX6x2Ifj29li/pQ9Wr4X3h/jHtBQ5LLLk0+9oITssuvG5A/VnBJRirnfcRUm8GAhO3ssE JIOaUirR1a5cEXb8flq3XFE3b0LHoojfJ3769eiGTZDuP3BosOf4qZjc8h4pSBiaEbfhxd802Rm alcODEBTpjc/kUrady07eaB4Wgn2XUV+j1Xm9511zR86joBW54olNSJ+lvl/zfR029dY7ME3KRs se84+cVGDers4CEiurCAHsmC1BeBYlp9M3xDjJFrDE2kSI9ObmzfG60Eys5V/6EfkPixX40z8sT DjlZADi7ZC/ntmWBSlku4jjIA2kGqTTdG4ah+7CZX00xxbcDhkeJLsOo99NNZeRsUZy14xowWbY +ffB4YWERABbP X-Developer-Key: i=duje.mihanovic@skole.hr; a=openpgp; fpr=53DF9D4D9C3FE110FB362D789A119EB0422D96E1 X-Endpoint-Received: by B4 Relay for duje.mihanovic@skole.hr/default with auth_id=112 X-Original-From: =?utf-8?q?Duje_Mihanovi=C4=87?= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240618_050920_647085_17FA4D8E X-CRM114-Status: GOOD ( 12.30 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: duje.mihanovic@skole.hr Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Duje Mihanović Add dt bindings and documentation for the Marvell PXA1908 clock controller. Reviewed-by: Conor Dooley Reviewed-by: Stephen Boyd Signed-off-by: Duje Mihanović --- .../devicetree/bindings/clock/marvell,pxa1908.yaml | 48 ++++++++++++ include/dt-bindings/clock/marvell,pxa1908.h | 88 ++++++++++++++++++++++ 2 files changed, 136 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml b/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml new file mode 100644 index 000000000000..4e78933232b6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/marvell,pxa1908.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell PXA1908 Clock Controllers + +maintainers: + - Duje Mihanović + +description: | + The PXA1908 clock subsystem generates and supplies clock to various + controllers within the PXA1908 SoC. The PXA1908 contains numerous clock + controller blocks, with the ones currently supported being APBC, APBCP, MPMU + and APMU roughly corresponding to internal buses. + + All these clock identifiers could be found in . + +properties: + compatible: + enum: + - marvell,pxa1908-apbc + - marvell,pxa1908-apbcp + - marvell,pxa1908-mpmu + - marvell,pxa1908-apmu + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + # APMU block: + - | + clock-controller@d4282800 { + compatible = "marvell,pxa1908-apmu"; + reg = <0xd4282800 0x400>; + #clock-cells = <1>; + }; diff --git a/include/dt-bindings/clock/marvell,pxa1908.h b/include/dt-bindings/clock/marvell,pxa1908.h new file mode 100644 index 000000000000..fb15b0d0cd4c --- /dev/null +++ b/include/dt-bindings/clock/marvell,pxa1908.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +#ifndef __DTS_MARVELL_PXA1908_CLOCK_H +#define __DTS_MARVELL_PXA1908_CLOCK_H + +/* plls */ +#define PXA1908_CLK_CLK32 1 +#define PXA1908_CLK_VCTCXO 2 +#define PXA1908_CLK_PLL1_624 3 +#define PXA1908_CLK_PLL1_416 4 +#define PXA1908_CLK_PLL1_499 5 +#define PXA1908_CLK_PLL1_832 6 +#define PXA1908_CLK_PLL1_1248 7 +#define PXA1908_CLK_PLL1_D2 8 +#define PXA1908_CLK_PLL1_D4 9 +#define PXA1908_CLK_PLL1_D8 10 +#define PXA1908_CLK_PLL1_D16 11 +#define PXA1908_CLK_PLL1_D6 12 +#define PXA1908_CLK_PLL1_D12 13 +#define PXA1908_CLK_PLL1_D24 14 +#define PXA1908_CLK_PLL1_D48 15 +#define PXA1908_CLK_PLL1_D96 16 +#define PXA1908_CLK_PLL1_D13 17 +#define PXA1908_CLK_PLL1_32 18 +#define PXA1908_CLK_PLL1_208 19 +#define PXA1908_CLK_PLL1_117 20 +#define PXA1908_CLK_PLL1_416_GATE 21 +#define PXA1908_CLK_PLL1_624_GATE 22 +#define PXA1908_CLK_PLL1_832_GATE 23 +#define PXA1908_CLK_PLL1_1248_GATE 24 +#define PXA1908_CLK_PLL1_D2_GATE 25 +#define PXA1908_CLK_PLL1_499_EN 26 +#define PXA1908_CLK_PLL2VCO 27 +#define PXA1908_CLK_PLL2 28 +#define PXA1908_CLK_PLL2P 29 +#define PXA1908_CLK_PLL2VCODIV3 30 +#define PXA1908_CLK_PLL3VCO 31 +#define PXA1908_CLK_PLL3 32 +#define PXA1908_CLK_PLL3P 33 +#define PXA1908_CLK_PLL3VCODIV3 34 +#define PXA1908_CLK_PLL4VCO 35 +#define PXA1908_CLK_PLL4 36 +#define PXA1908_CLK_PLL4P 37 +#define PXA1908_CLK_PLL4VCODIV3 38 + +/* apb (apbc) peripherals */ +#define PXA1908_CLK_UART0 1 +#define PXA1908_CLK_UART1 2 +#define PXA1908_CLK_GPIO 3 +#define PXA1908_CLK_PWM0 4 +#define PXA1908_CLK_PWM1 5 +#define PXA1908_CLK_PWM2 6 +#define PXA1908_CLK_PWM3 7 +#define PXA1908_CLK_SSP0 8 +#define PXA1908_CLK_SSP1 9 +#define PXA1908_CLK_IPC_RST 10 +#define PXA1908_CLK_RTC 11 +#define PXA1908_CLK_TWSI0 12 +#define PXA1908_CLK_KPC 13 +#define PXA1908_CLK_SWJTAG 14 +#define PXA1908_CLK_SSP2 15 +#define PXA1908_CLK_TWSI1 16 +#define PXA1908_CLK_THERMAL 17 +#define PXA1908_CLK_TWSI3 18 + +/* apb (apbcp) peripherals */ +#define PXA1908_CLK_UART2 1 +#define PXA1908_CLK_TWSI2 2 +#define PXA1908_CLK_AICER 3 + +/* axi (apmu) peripherals */ +#define PXA1908_CLK_CCIC1 1 +#define PXA1908_CLK_ISP 2 +#define PXA1908_CLK_DSI1 3 +#define PXA1908_CLK_DISP1 4 +#define PXA1908_CLK_CCIC0 5 +#define PXA1908_CLK_SDH0 6 +#define PXA1908_CLK_SDH1 7 +#define PXA1908_CLK_USB 8 +#define PXA1908_CLK_NF 9 +#define PXA1908_CLK_CORE_DEBUG 10 +#define PXA1908_CLK_VPU 11 +#define PXA1908_CLK_GC 12 +#define PXA1908_CLK_SDH2 13 +#define PXA1908_CLK_GC2D 14 +#define PXA1908_CLK_TRACE 15 +#define PXA1908_CLK_DVC_DFC_DEBUG 16 + +#endif