| Message ID | 20240618164133.223194-2-linux.amoon@gmail.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [v1,1/3] PCI: rockchip: Simplify clock handling by using clk_bulk*() function | expand |
Hi Anand, kernel test robot noticed the following build errors: [auto build test ERROR on pci/next] [also build test ERROR on pci/for-linus linus/master v6.10-rc4 next-20240619] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Anand-Moon/PCI-rockchip-Simplify-reset-control-handling-by-using-reset_control_bulk-function/20240619-014145 base: https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next patch link: https://lore.kernel.org/r/20240618164133.223194-2-linux.amoon%40gmail.com patch subject: [PATCH v1 1/3] PCI: rockchip: Simplify clock handling by using clk_bulk*() function config: arc-randconfig-001-20240620 (https://download.01.org/0day-ci/archive/20240620/202406200818.CQ7DXNSZ-lkp@intel.com/config) compiler: arceb-elf-gcc (GCC) 13.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240620/202406200818.CQ7DXNSZ-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202406200818.CQ7DXNSZ-lkp@intel.com/ All errors (new ones prefixed by >>): In file included from drivers/pci/controller/pcie-rockchip-ep.c:20: >> drivers/pci/controller/pcie-rockchip.h:311:31: error: array type has incomplete element type 'struct clk_bulk_data' 311 | struct clk_bulk_data clks[ROCKCHIP_NUM_CLKS]; | ^~~~ vim +311 drivers/pci/controller/pcie-rockchip.h 298 299 struct rockchip_pcie { 300 void __iomem *reg_base; /* DT axi-base */ 301 void __iomem *apb_base; /* DT apb-base */ 302 bool legacy_phy; 303 struct phy *phys[MAX_LANE_NUM]; 304 struct reset_control *core_rst; 305 struct reset_control *mgmt_rst; 306 struct reset_control *mgmt_sticky_rst; 307 struct reset_control *pipe_rst; 308 struct reset_control *pm_rst; 309 struct reset_control *aclk_rst; 310 struct reset_control *pclk_rst; > 311 struct clk_bulk_data clks[ROCKCHIP_NUM_CLKS]; 312 struct regulator *vpcie12v; /* 12V power supply */ 313 struct regulator *vpcie3v3; /* 3.3V power supply */ 314 struct regulator *vpcie1v8; /* 1.8V power supply */ 315 struct regulator *vpcie0v9; /* 0.9V power supply */ 316 struct gpio_desc *ep_gpio; 317 u32 lanes; 318 u8 lanes_map; 319 int link_gen; 320 struct device *dev; 321 struct irq_domain *irq_domain; 322 int offset; 323 void __iomem *msg_region; 324 phys_addr_t msg_bus_addr; 325 bool is_rc; 326 struct resource *mem_res; 327 }; 328
Hi All, On Thu, 20 Jun 2024 at 06:25, kernel test robot <lkp@intel.com> wrote: > > Hi Anand, > > kernel test robot noticed the following build errors: > > [auto build test ERROR on pci/next] > [also build test ERROR on pci/for-linus linus/master v6.10-rc4 next-20240619] > [If your patch is applied to the wrong git tree, kindly drop us a note. > And when submitting patch, we suggest to use '--base' as documented in > https://git-scm.com/docs/git-format-patch#_base_tree_information] > > url: https://github.com/intel-lab-lkp/linux/commits/Anand-Moon/PCI-rockchip-Simplify-reset-control-handling-by-using-reset_control_bulk-function/20240619-014145 > base: https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next > patch link: https://lore.kernel.org/r/20240618164133.223194-2-linux.amoon%40gmail.com > patch subject: [PATCH v1 1/3] PCI: rockchip: Simplify clock handling by using clk_bulk*() function > config: arc-randconfig-001-20240620 (https://download.01.org/0day-ci/archive/20240620/202406200818.CQ7DXNSZ-lkp@intel.com/config) > compiler: arceb-elf-gcc (GCC) 13.2.0 > reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240620/202406200818.CQ7DXNSZ-lkp@intel.com/reproduce) > > If you fix the issue in a separate patch/commit (i.e. not just a new version of > the same patch/commit), kindly add following tags > | Reported-by: kernel test robot <lkp@intel.com> > | Closes: https://lore.kernel.org/oe-kbuild-all/202406200818.CQ7DXNSZ-lkp@intel.com/ > > All errors (new ones prefixed by >>): > > In file included from drivers/pci/controller/pcie-rockchip-ep.c:20: > >> drivers/pci/controller/pcie-rockchip.h:311:31: error: array type has incomplete element type 'struct clk_bulk_data' > 311 | struct clk_bulk_data clks[ROCKCHIP_NUM_CLKS]; > | ^~~~ > I will try to fix this issue in the next version, once I get more feedback on the rest of the changes. > > vim +311 drivers/pci/controller/pcie-rockchip.h > > 298 > 299 struct rockchip_pcie { > 300 void __iomem *reg_base; /* DT axi-base */ > 301 void __iomem *apb_base; /* DT apb-base */ > 302 bool legacy_phy; > 303 struct phy *phys[MAX_LANE_NUM]; > 304 struct reset_control *core_rst; > 305 struct reset_control *mgmt_rst; > 306 struct reset_control *mgmt_sticky_rst; > 307 struct reset_control *pipe_rst; > 308 struct reset_control *pm_rst; > 309 struct reset_control *aclk_rst; > 310 struct reset_control *pclk_rst; > > 311 struct clk_bulk_data clks[ROCKCHIP_NUM_CLKS]; > 312 struct regulator *vpcie12v; /* 12V power supply */ > 313 struct regulator *vpcie3v3; /* 3.3V power supply */ > 314 struct regulator *vpcie1v8; /* 1.8V power supply */ > 315 struct regulator *vpcie0v9; /* 0.9V power supply */ > 316 struct gpio_desc *ep_gpio; > 317 u32 lanes; > 318 u8 lanes_map; > 319 int link_gen; > 320 struct device *dev; > 321 struct irq_domain *irq_domain; > 322 int offset; > 323 void __iomem *msg_region; > 324 phys_addr_t msg_bus_addr; > 325 bool is_rc; > 326 struct resource *mem_res; > 327 }; > 328 > > -- > 0-DAY CI Kernel Test Service > https://github.com/intel/lkp-tests/wiki Thanks -Anand
Hi Anand, kernel test robot noticed the following build errors: [auto build test ERROR on pci/next] [also build test ERROR on pci/for-linus linus/master v6.10-rc4 next-20240619] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Anand-Moon/PCI-rockchip-Simplify-reset-control-handling-by-using-reset_control_bulk-function/20240619-014145 base: https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next patch link: https://lore.kernel.org/r/20240618164133.223194-2-linux.amoon%40gmail.com patch subject: [PATCH v1 1/3] PCI: rockchip: Simplify clock handling by using clk_bulk*() function config: x86_64-allyesconfig (https://download.01.org/0day-ci/archive/20240621/202406210131.rxenHeBG-lkp@intel.com/config) compiler: clang version 18.1.5 (https://github.com/llvm/llvm-project 617a15a9eac96088ae5e9134248d8236e34b91b1) reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240621/202406210131.rxenHeBG-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202406210131.rxenHeBG-lkp@intel.com/ All errors (new ones prefixed by >>): In file included from drivers/pci/controller/pcie-rockchip-ep.c:20: >> drivers/pci/controller/pcie-rockchip.h:311:28: error: array has incomplete element type 'struct clk_bulk_data' 311 | struct clk_bulk_data clks[ROCKCHIP_NUM_CLKS]; | ^ drivers/pci/controller/pcie-rockchip.h:311:10: note: forward declaration of 'struct clk_bulk_data' 311 | struct clk_bulk_data clks[ROCKCHIP_NUM_CLKS]; | ^ 1 error generated. vim +311 drivers/pci/controller/pcie-rockchip.h 298 299 struct rockchip_pcie { 300 void __iomem *reg_base; /* DT axi-base */ 301 void __iomem *apb_base; /* DT apb-base */ 302 bool legacy_phy; 303 struct phy *phys[MAX_LANE_NUM]; 304 struct reset_control *core_rst; 305 struct reset_control *mgmt_rst; 306 struct reset_control *mgmt_sticky_rst; 307 struct reset_control *pipe_rst; 308 struct reset_control *pm_rst; 309 struct reset_control *aclk_rst; 310 struct reset_control *pclk_rst; > 311 struct clk_bulk_data clks[ROCKCHIP_NUM_CLKS]; 312 struct regulator *vpcie12v; /* 12V power supply */ 313 struct regulator *vpcie3v3; /* 3.3V power supply */ 314 struct regulator *vpcie1v8; /* 1.8V power supply */ 315 struct regulator *vpcie0v9; /* 0.9V power supply */ 316 struct gpio_desc *ep_gpio; 317 u32 lanes; 318 u8 lanes_map; 319 int link_gen; 320 struct device *dev; 321 struct irq_domain *irq_domain; 322 int offset; 323 void __iomem *msg_region; 324 phys_addr_t msg_bus_addr; 325 bool is_rc; 326 struct resource *mem_res; 327 }; 328
diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c index 0ef2e622d36e..166dad666a35 100644 --- a/drivers/pci/controller/pcie-rockchip.c +++ b/drivers/pci/controller/pcie-rockchip.c @@ -30,7 +30,7 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) struct platform_device *pdev = to_platform_device(dev); struct device_node *node = dev->of_node; struct resource *regs; - int err; + int err, i; if (rockchip->is_rc) { regs = platform_get_resource_byname(pdev, @@ -127,28 +127,13 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) "failed to get ep GPIO\n"); } - rockchip->aclk_pcie = devm_clk_get(dev, "aclk"); - if (IS_ERR(rockchip->aclk_pcie)) { - dev_err(dev, "aclk clock not found\n"); - return PTR_ERR(rockchip->aclk_pcie); - } - - rockchip->aclk_perf_pcie = devm_clk_get(dev, "aclk-perf"); - if (IS_ERR(rockchip->aclk_perf_pcie)) { - dev_err(dev, "aclk_perf clock not found\n"); - return PTR_ERR(rockchip->aclk_perf_pcie); - } - - rockchip->hclk_pcie = devm_clk_get(dev, "hclk"); - if (IS_ERR(rockchip->hclk_pcie)) { - dev_err(dev, "hclk clock not found\n"); - return PTR_ERR(rockchip->hclk_pcie); - } + for (i = 0; i < ROCKCHIP_NUM_CLKS; i++) + rockchip->clks[i].id = rockchip_pci_clks[i]; - rockchip->clk_pcie_pm = devm_clk_get(dev, "pm"); - if (IS_ERR(rockchip->clk_pcie_pm)) { - dev_err(dev, "pm clock not found\n"); - return PTR_ERR(rockchip->clk_pcie_pm); + err = devm_clk_bulk_get(dev, ROCKCHIP_NUM_CLKS, rockchip->clks); + if (err) { + dev_err(dev, "rockchip clk bulk get failed\n"); + return err; } return 0; @@ -372,39 +357,13 @@ int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip) struct device *dev = rockchip->dev; int err; - err = clk_prepare_enable(rockchip->aclk_pcie); + err = clk_bulk_prepare_enable(ROCKCHIP_NUM_CLKS, rockchip->clks); if (err) { - dev_err(dev, "unable to enable aclk_pcie clock\n"); + dev_err(dev, "rockchip clk bulk prepare enable failed\n"); return err; } - err = clk_prepare_enable(rockchip->aclk_perf_pcie); - if (err) { - dev_err(dev, "unable to enable aclk_perf_pcie clock\n"); - goto err_aclk_perf_pcie; - } - - err = clk_prepare_enable(rockchip->hclk_pcie); - if (err) { - dev_err(dev, "unable to enable hclk_pcie clock\n"); - goto err_hclk_pcie; - } - - err = clk_prepare_enable(rockchip->clk_pcie_pm); - if (err) { - dev_err(dev, "unable to enable clk_pcie_pm clock\n"); - goto err_clk_pcie_pm; - } - return 0; - -err_clk_pcie_pm: - clk_disable_unprepare(rockchip->hclk_pcie); -err_hclk_pcie: - clk_disable_unprepare(rockchip->aclk_perf_pcie); -err_aclk_perf_pcie: - clk_disable_unprepare(rockchip->aclk_pcie); - return err; } EXPORT_SYMBOL_GPL(rockchip_pcie_enable_clocks); @@ -412,10 +371,7 @@ void rockchip_pcie_disable_clocks(void *data) { struct rockchip_pcie *rockchip = data; - clk_disable_unprepare(rockchip->clk_pcie_pm); - clk_disable_unprepare(rockchip->hclk_pcie); - clk_disable_unprepare(rockchip->aclk_perf_pcie); - clk_disable_unprepare(rockchip->aclk_pcie); + clk_bulk_disable_unprepare(ROCKCHIP_NUM_CLKS, rockchip->clks); } EXPORT_SYMBOL_GPL(rockchip_pcie_disable_clocks); diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h index 6111de35f84c..f256cdf4fa49 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -287,6 +287,15 @@ (((c) << ((b) * 8 + 5)) & \ ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)) +#define ROCKCHIP_NUM_CLKS ARRAY_SIZE(rockchip_pci_clks) + +static const char * const rockchip_pci_clks[] = { + "aclk", + "aclk-perf", + "hclk", + "pm", +}; + struct rockchip_pcie { void __iomem *reg_base; /* DT axi-base */ void __iomem *apb_base; /* DT apb-base */ @@ -299,10 +308,7 @@ struct rockchip_pcie { struct reset_control *pm_rst; struct reset_control *aclk_rst; struct reset_control *pclk_rst; - struct clk *aclk_pcie; - struct clk *aclk_perf_pcie; - struct clk *hclk_pcie; - struct clk *clk_pcie_pm; + struct clk_bulk_data clks[ROCKCHIP_NUM_CLKS]; struct regulator *vpcie12v; /* 12V power supply */ struct regulator *vpcie3v3; /* 3.3V power supply */ struct regulator *vpcie1v8; /* 1.8V power supply */
Refactors the clock handling in the Rockchip PCIe driver, introducing a more robust and efficient method for enabling and disabling clocks using clk_bulk*() API. Using the clk_bulk APIs, the clock handling for the core clocks becomes much simpler. Signed-off-by: Anand Moon <linux.amoon@gmail.com> --- drivers/pci/controller/pcie-rockchip.c | 64 ++++---------------------- drivers/pci/controller/pcie-rockchip.h | 14 ++++-- 2 files changed, 20 insertions(+), 58 deletions(-)