diff mbox series

[3/3] arm64: dts: ti: k3-j722s: Add gpio-ranges properties

Message ID 20240618173123.2592074-4-nm@ti.com (mailing list archive)
State New
Headers show
Series arm64: dts: ti: k3-am62p/j722s: Add gpio-ranges properties | expand

Commit Message

Nishanth Menon June 18, 2024, 5:31 p.m. UTC 
From: Jared McArthur <j-mcarthur@ti.com>

The AM67A/J722S/TDA4AEN platform is a derivative of AM62P platform
and we have no single 1:1 relation regarding index of GPIO and pin
controller. The GPIOs and pin controller registers have mapping and
holes in the map. These have been extracted from the J722S data
sheet. The MCU mapping is carried forward as is with J722S, however the
main GPIO block has differences that needs to be accounted for.

Mux mode input is selected as it is bi-directional. In case a specific
pull type or a specific pin level drive setting is desired, the board
device tree files will have to explicitly mux those pins for the GPIO
with the desired setting.

Ref: J722S Data sheet https://www.ti.com/lit/gpn/tda4aen-q1

Signed-off-by: Jared McArthur <j-mcarthur@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
---

Note: this generates a 'too large' warning for
pinctrl-single,gpio-ranges -
https://lore.kernel.org/r/20240618165102.2380159-1-nm@ti.com/ for more
details

 arch/arm64/boot/dts/ti/k3-j722s.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
index 9132b0232b0b..84441a8ed4f0 100644
--- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
@@ -83,11 +83,28 @@  &inta_main_dmss {
 	ti,interrupt-ranges = <7 71 21>;
 };
 
+&main_pmx0 {
+	pinctrl-single,gpio-range =
+		<&main_pmx0_range 0 32 (PIN_INPUT | PIN_GPIO_MUX_MODE)>,
+		<&main_pmx0_range 33 55 (PIN_INPUT | PIN_GPIO_MUX_MODE)>,
+		<&main_pmx0_range 101 25 (PIN_INPUT | PIN_GPIO_MUX_MODE)>,
+		<&main_pmx0_range 137 5 (PIN_INPUT | PIN_GPIO_MUX_MODE)>,
+		<&main_pmx0_range 143 3 (PIN_INPUT | PIN_GPIO_MUX_MODE)>,
+		<&main_pmx0_range 149 2 (PIN_INPUT | PIN_GPIO_MUX_MODE)>;
+};
+
 &main_gpio0 {
+	gpio-ranges = <&main_pmx0 0 0 32>,
+		      <&main_pmx0 32 33 38>,
+		      <&main_pmx0 70 72 17>;
 	ti,ngpio = <87>;
 };
 
 &main_gpio1 {
+	gpio-ranges = <&main_pmx0 7 101 25>,
+		      <&main_pmx0 42 137 5>,
+		      <&main_pmx0 47 143 3>,
+		      <&main_pmx0 50 149 2>;
 	ti,ngpio = <73>;
 };