From patchwork Thu Jun 20 07:37:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 13704916 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 062C2C2BB85 for ; Thu, 20 Jun 2024 07:37:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:To: From:Reply-To:Cc:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=20CA5prDqUxWAM1Z+Eol6q+Z786udVSKpzg64UmQk+s=; b=tCV9z8y95IIX7d/reXEu9ijqgh bH98UhGHg3k++Zq9bzSjnWyESAY8LGfL9Tygyrl8vdvEejoHDerbaoYPI7LjtUmqs4vNhBctOKgt6 vE+bynwUg3LGXQbz/NtqE/rsluFRqdlpT0TOS1o5VZiLK+iNuKxIKjBf1ZohYSUfj3JR1gfObJifb myja0RNrV7JGG+3P15W1ym/KFxrfu/xarp17I8aADW8kVpdE7t50vlENFa/XcWXTVNdtjR2Q2JSD0 W2IuTTAbP+FgxcInIMncDsJHf22M3+Pg3e3YSPVa8JlyOpEMyGSmFIbr7c8mrZ5dYaUKhr+E2sIz9 kkkBB1sQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sKCMN-000000040Zz-1LAp; Thu, 20 Jun 2024 07:37:31 +0000 Received: from sin.source.kernel.org ([145.40.73.55]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sKCMJ-000000040Yd-1nDG for linux-arm-kernel@lists.infradead.org; Thu, 20 Jun 2024 07:37:28 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id AA112CE23BA; Thu, 20 Jun 2024 07:37:25 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id CEB78C32781; Thu, 20 Jun 2024 07:37:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1718869044; bh=WPti5GNnym1yh8L19XY39E6BdWNRYNdoXbDLMmL10TM=; h=From:To:Subject:Date:In-Reply-To:References:From; b=NyBMFnFsj3Z2b2D2EIng2YfvMiwQf+AcjLhRdCceNC/YE6AuGmO3OJCCmygZK7wJI Yij/NKj7kMEaOlsE9JzjqVs2PPG/TbVK3gOyfpPOh4RthIdsk67A57XMSOXhBt8l/6 GCpzasGyvXMPgjjY3h0VZWr8Vdpk759AcS5+YdWSdgi+FlMTMunKDW28YW94HIfSC4 I1gtLMNKwcjOmL85i4p9JhE7ta/x0ejBjqaq1jymjqFnqG1XBKbHcm/U/5wF0Vb/EQ 3Vc/on9i8oMzwqdMQslkYc2MnAFItIt4ZmITr8HinU7pbGMGmxWOBWfk6BjubtLVMM ZfZJaT7bhzdYg== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, arm@kernel.org, Andy Shevchenko , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Subject: [PATCH v2 2/4] irqchip/armada-370-xp: Only call ipi_resume() if IPI is available Date: Thu, 20 Jun 2024 09:37:13 +0200 Message-ID: <20240620073715.13560-3-kabel@kernel.org> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240620073715.13560-1-kabel@kernel.org> References: <20240620073715.13560-1-kabel@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240620_003727_676310_43F9E40C X-CRM114-Status: GOOD ( 13.66 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Pali Rohár IPI is available only on systems where the mpic controller does not have a parent IRQ defined (e.g. on Armada XP). If a parent IRQ is defined, inter-processor interrupts are handled by an interrupt controller higher in the hierarchy (most probably a parent GIC). Only call ipi_resume() on systems where IPI is available in the mpic controller. Signed-off-by: Pali Rohár [ refactored a little and changed commit message ] Signed-off-by: Marek Behún Reviewed-by: Andrew Lunn --- drivers/irqchip/irq-armada-370-xp.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c index f488c35d9130..ea95e327f672 100644 --- a/drivers/irqchip/irq-armada-370-xp.c +++ b/drivers/irqchip/irq-armada-370-xp.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -156,6 +157,17 @@ static DEFINE_MUTEX(msi_used_lock); static phys_addr_t msi_doorbell_addr; #endif +static inline bool is_ipi_available(void) +{ + /* + * We distinguish IPI availability in the IC by the IC not having a + * parent irq defined. If a parent irq is defined, there is a parent + * interrupt controller (e.g. GIC) that takes care of inter-processor + * interrupts. + */ + return parent_irq <= 0; +} + static inline bool is_percpu_irq(irq_hw_number_t irq) { if (irq <= ARMADA_370_XP_MAX_PER_CPU_IRQS) @@ -527,7 +539,8 @@ static void armada_xp_mpic_reenable_percpu(void) armada_370_xp_irq_unmask(data); } - ipi_resume(); + if (is_ipi_available()) + ipi_resume(); armada_370_xp_msi_reenable_percpu(); } @@ -750,7 +763,8 @@ static void armada_370_xp_mpic_resume(void) if (doorbell_mask_reg & PCI_MSI_DOORBELL_MASK) writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); - ipi_resume(); + if (is_ipi_available()) + ipi_resume(); } static struct syscore_ops armada_370_xp_mpic_syscore_ops = {