@@ -86,6 +86,7 @@ enum power_event {
#define GMAC_RGSMIIIS 0x000000d8 /* RGMII/SMII status */
/* SGMII/RGMII status register */
+#define GMAC_RGSMIIIS_CONFIG_REG GENMASK(15, 0)
#define GMAC_RGSMIIIS_LNKMODE BIT(0)
#define GMAC_RGSMIIIS_SPEED GENMASK(2, 1)
#define GMAC_RGSMIIIS_SPEED_SHIFT 1
@@ -365,6 +365,16 @@ static void dwmac1000_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
writel(value, ioaddr + LPI_TIMER_CTRL);
}
+static u16 dwmac1000_pcs_get_config_reg(struct mac_device_info *hw)
+{
+ void __iomem *ioaddr = hw->pcsr;
+ u32 val;
+
+ val = readl(ioaddr + GMAC_RGSMIIIS);
+
+ return FIELD_GET(GMAC_RGSMIIIS_CONFIG_REG, val);
+}
+
static void dwmac1000_ctrl_ane(void __iomem *pcsaddr, bool ane, bool srgmi_ral,
bool loopback)
{
@@ -568,6 +578,7 @@ const struct stmmac_ops dwmac1000_ops = {
.set_eee_timer = dwmac1000_set_eee_timer,
.set_eee_pls = dwmac1000_set_eee_pls,
.debug = dwmac1000_debug,
+ .pcs_get_config_reg = dwmac1000_pcs_get_config_reg,
.pcs_ctrl_ane = dwmac1000_ctrl_ane,
.set_mac_loopback = dwmac1000_set_mac_loopback,
};
@@ -567,6 +567,7 @@ static inline u32 mtl_low_credx_base_addr(const struct dwmac4_addrs *addrs,
#define GMAC_PHYIF_CTRLSTATUS_TC BIT(0)
#define GMAC_PHYIF_CTRLSTATUS_LUD BIT(1)
#define GMAC_PHYIF_CTRLSTATUS_SMIDRXS BIT(4)
+#define GMAC_PHYIF_CTRLSTATUS_CONFIG_REG GENMASK(31, 16)
#define GMAC_PHYIF_CTRLSTATUS_LNKMOD BIT(16)
#define GMAC_PHYIF_CTRLSTATUS_SPEED GENMASK(18, 17)
#define GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT 17
@@ -456,6 +456,16 @@ static void dwmac4_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
writel(value, ioaddr + GMAC4_LPI_TIMER_CTRL);
}
+static u16 dwmac4_pcs_get_config_reg(struct mac_device_info *hw)
+{
+ void __iomem *ioaddr = hw->pcsr;
+ u32 val;
+
+ val = readl(ioaddr + GMAC_PHYIF_CONTROL_STATUS);
+
+ return FIELD_GET(GMAC_PHYIF_CTRLSTATUS_CONFIG_REG, val);
+}
+
static void dwmac4_write_single_vlan(struct net_device *dev, u16 vid)
{
void __iomem *ioaddr = (void __iomem *)dev->base_addr;
@@ -1274,6 +1284,7 @@ const struct stmmac_ops dwmac4_ops = {
.set_eee_pls = dwmac4_set_eee_pls,
.pcs_ctrl_ane = dwmac4_ctrl_ane,
.debug = dwmac4_debug,
+ .pcs_get_config_reg = dwmac4_pcs_get_config_reg,
.set_filter = dwmac4_set_filter,
.set_mac_loopback = dwmac4_set_mac_loopback,
.update_vlan_hash = dwmac4_update_vlan_hash,
@@ -1318,6 +1329,7 @@ const struct stmmac_ops dwmac410_ops = {
.set_eee_pls = dwmac4_set_eee_pls,
.pcs_ctrl_ane = dwmac4_ctrl_ane,
.debug = dwmac4_debug,
+ .pcs_get_config_reg = dwmac4_pcs_get_config_reg,
.set_filter = dwmac4_set_filter,
.flex_pps_config = dwmac5_flex_pps_config,
.set_mac_loopback = dwmac4_set_mac_loopback,
@@ -1366,6 +1378,7 @@ const struct stmmac_ops dwmac510_ops = {
.set_eee_pls = dwmac4_set_eee_pls,
.pcs_ctrl_ane = dwmac4_ctrl_ane,
.debug = dwmac4_debug,
+ .pcs_get_config_reg = dwmac4_pcs_get_config_reg,
.set_filter = dwmac4_set_filter,
.safety_feat_config = dwmac5_safety_feat_config,
.safety_feat_irq_status = dwmac5_safety_feat_irq_status,
@@ -376,6 +376,7 @@ struct stmmac_ops {
struct stmmac_extra_stats *x, u32 rx_queues,
u32 tx_queues);
/* PCS calls */
+ u16 (*pcs_get_config_reg)(struct mac_device_info *hw);
void (*pcs_ctrl_ane)(void __iomem *pcsaddr, bool ane, bool srgmi_ral,
bool loopback);
/* Safety Features */
@@ -492,6 +493,8 @@ struct stmmac_ops {
stmmac_do_void_callback(__priv, mac, set_eee_pls, __args)
#define stmmac_mac_debug(__priv, __args...) \
stmmac_do_void_callback(__priv, mac, debug, __priv, __args)
+#define stmmac_pcs_get_config_reg(__priv, __args...) \
+ stmmac_do_callback(__priv, mac, pcs_get_config_reg, __args)
#define stmmac_pcs_ctrl_ane(__priv, __args...) \
stmmac_do_void_callback(__priv, mac, pcs_ctrl_ane, __args)
#define stmmac_safety_feat_config(__priv, __args...) \
The optional PCS module CSRs are mainly represented in the framework of the address spaces [0x00c0:0x00db] on DW GMAC and [0x00e0:0x00f7] on DW QoS Eth. The spaces mapping is identical in both IP-cores. But the link state retrieved from the PHY or from another MAC (in MAC2MAC setup) is mapped over the SGMII/RGMII/SMII Control and Status register in a non-compatible way. In particular the DW GMAC register have the link state mapped at the [15:0] field, and the DW QoS Eth register have it mapped at the [31:16] field. Other than that the fields semantics is identical - it's the TX_CONFIG_REG[15:0] register (see SGMII specification for details) with a bit re-ordered fields and extended with some SMII-specific flags: tx_config_reg[0]: LNKMOD tx_config_reg[1:2]: LNKSPEED tx_config_reg[3]: LNKSTS tx_config_reg[4]: JABTO (Jabber Timeout, SMII-specific) tx_config_reg[5]: FALSCARDET (False Carrier Detected, SMII-specific) In order to provide a fully generic internal STMMAC PCS module, let's introduce the MAC-specific callback returning the link state detected by the internal PCS. Note the callback name has been chosen to be referring to the TX_CONFIG_REG data described in the IP-core databooks and in the SGMII specification. Signed-off-by: Serge Semin <fancer.lancer@gmail.com> --- drivers/net/ethernet/stmicro/stmmac/dwmac1000.h | 1 + .../net/ethernet/stmicro/stmmac/dwmac1000_core.c | 11 +++++++++++ drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 1 + drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c | 13 +++++++++++++ drivers/net/ethernet/stmicro/stmmac/hwif.h | 3 +++ 5 files changed, 29 insertions(+)