From patchwork Wed Jun 26 22:32:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 13713491 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9CDF3C27C4F for ; Wed, 26 Jun 2024 22:33:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References :Message-Id:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=XqZIJ8mKk/jH5TsN1IAW/WwpkbOn2CQYrZkga3yovkc=; b=dgpo3mdScEb+6Gunwg+0BN2n+Q h57UCW5xfEfYSt8Plod4YYdhgZE6ZsflelGZQouMuNDvSsSSOpt/By3dO9Qitqcq0AXKqgUis9HBE Ddcbk/13tFcgcvbgVCgLOotjf/eZsXYFgKexztI+YW6nYlUqIHY5CYxIwQVySNgfA5zd0yEPDyOdt pu1y9zyYkovr+6aVyhNfnRzCVcgf73MCz7omlpvnIp5GBaMTI6v6NIpu79Ov6NdatLfCTUs5AOy7q eVHPA7GOkRKa8R9tUwJOZWFreoN6alI7pN5HK1URbBv+3mx2Ohq0gfclkezP7JdN91IkNqFPJminR pOwRDHxA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sMbCF-00000008VaP-0K6T; Wed, 26 Jun 2024 22:32:59 +0000 Received: from sin.source.kernel.org ([145.40.73.55]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sMbBw-00000008VNv-443h for linux-arm-kernel@lists.infradead.org; Wed, 26 Jun 2024 22:32:42 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id 0A1FCCE2CB6; Wed, 26 Jun 2024 22:32:39 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 702F4C32789; Wed, 26 Jun 2024 22:32:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1719441158; bh=acEqJRld4aaAwF/FQV6CD2Di0ENXDKGblEFIRkrSSxI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=udeLf8lZU5JtyXeXK3aJgJ5ZFbKUGK3E/HBlBD7PSQwzvahYPQlr0gAA478XGid05 JWAJD0UfpyT8nburYYBEQciFf1rYIA+QhkiBKD9eV7hTAwVoQxYL5eEhDQu/DNvTAg uh9MHE9SqAQWPA0D+5Nf5N0MZviQKrlEst0s2XiSmnCPboiDDgUpy7YHDOlz2MQgBO vfJEAICL6wB1WayJxlq4aMXAawaoomlm0U658P88UTmkgzX/SXspLQTF/qOxdaY73p UKkS5yC/yez+ltLDgSRYCn9MMe+RrUsbTUiHzmREIgxYcGyQlyXq7C+8j8Cug7MtRW 9AOZf8kYYRyJg== From: "Rob Herring (Arm)" Date: Wed, 26 Jun 2024 16:32:25 -0600 Subject: [PATCH v2 01/12] perf: arm_pmuv3: Avoid assigning fixed cycle counter with threshold MIME-Version: 1.0 Message-Id: <20240626-arm-pmu-3-9-icntr-v2-1-c9784b4f4065@kernel.org> References: <20240626-arm-pmu-3-9-icntr-v2-0-c9784b4f4065@kernel.org> In-Reply-To: <20240626-arm-pmu-3-9-icntr-v2-0-c9784b4f4065@kernel.org> To: Russell King , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , James Clark Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, kvmarm@lists.linux.dev X-Mailer: b4 0.14-dev X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240626_153241_407962_D190858F X-CRM114-Status: GOOD ( 15.69 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org If the user has requested a counting threshold for the CPU cycles event, then the fixed cycle counter can't be assigned as it lacks threshold support. Currently, the thresholds will work or not randomly depending on which counter the event is assigned. While using thresholds for CPU cycles doesn't make much sense, it can be useful for testing purposes. Fixes: 816c26754447 ("arm64: perf: Add support for event counting threshold") Signed-off-by: Rob Herring (Arm) Acked-by: Mark Rutland --- This should go to 6.10 and stable. It is also a dependency for ICNTR support. v2: - Add and use armv8pmu_event_get_threshold() helper. v1: https://lore.kernel.org/all/20240611155012.2286044-1-robh@kernel.org/ --- drivers/perf/arm_pmuv3.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c index 23fa6c5da82c..8ed5c3358920 100644 --- a/drivers/perf/arm_pmuv3.c +++ b/drivers/perf/arm_pmuv3.c @@ -338,6 +338,11 @@ static bool armv8pmu_event_want_user_access(struct perf_event *event) return ATTR_CFG_GET_FLD(&event->attr, rdpmc); } +static u32 armv8pmu_event_get_threshold(struct perf_event_attr *attr) +{ + return ATTR_CFG_GET_FLD(attr, threshold); +} + static u8 armv8pmu_event_threshold_control(struct perf_event_attr *attr) { u8 th_compare = ATTR_CFG_GET_FLD(attr, threshold_compare); @@ -941,7 +946,8 @@ static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc, unsigned long evtype = hwc->config_base & ARMV8_PMU_EVTYPE_EVENT; /* Always prefer to place a cycle counter into the cycle counter. */ - if (evtype == ARMV8_PMUV3_PERFCTR_CPU_CYCLES) { + if ((evtype == ARMV8_PMUV3_PERFCTR_CPU_CYCLES) && + !armv8pmu_event_get_threshold(&event->attr)) { if (!test_and_set_bit(ARMV8_IDX_CYCLE_COUNTER, cpuc->used_mask)) return ARMV8_IDX_CYCLE_COUNTER; else if (armv8pmu_event_is_64bit(event) && @@ -1033,7 +1039,7 @@ static int armv8pmu_set_event_filter(struct hw_perf_event *event, * If FEAT_PMUv3_TH isn't implemented, then THWIDTH (threshold_max) will * be 0 and will also trigger this check, preventing it from being used. */ - th = ATTR_CFG_GET_FLD(attr, threshold); + th = armv8pmu_event_get_threshold(attr); if (th > threshold_max(cpu_pmu)) { pr_debug("PMU event threshold exceeds max value\n"); return -EINVAL;