From patchwork Mon Jul 1 17:02:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 13718463 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C8C3DC2BD09 for ; Mon, 1 Jul 2024 17:06:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc: To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=ai9Lwe2I+wbODqMKwjl/3jXhC5hxrcvswITzp2Ku3cQ=; b=Sa1ZS/hzHntUt6OgDUUvIYmCgx 7+lfC+VYtN2nd0UqVxhAhkqNZFEoTMp48MMPJ1x8FXv9zXP2ZJXif9ImEMwZBi0FOJkaTBN1cfOf8 jKadC4p4kxNEuB9YHieMlj7RhM8nD/TsoO2gPoPa5i7hDgInbD8YH6FpH/C/HtY3H8lltVsCLZyRv zY/cYwTVc2p2ic3/uTlx9siy7hOOkKxBwHLWo7HiP/L/qRdNndpPSAZCYz79DELClBhSnbHIk3hLh W1t0zgrLSH7BdghznGm+6bc/3DHaZGejRbSBojeVMYUACygOgMQxvW/3W37vpT2cmOpe7usG2tT22 VbDUvZgA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sOKTe-00000004ErG-16q9; Mon, 01 Jul 2024 17:06:06 +0000 Received: from sin.source.kernel.org ([145.40.73.55]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sOKRT-00000004Dhu-063t for linux-arm-kernel@lists.infradead.org; Mon, 01 Jul 2024 17:03:52 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id 27254CE1A4F; Mon, 1 Jul 2024 17:03:48 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E9275C116B1; Mon, 1 Jul 2024 17:03:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1719853427; bh=hmwLBtLORKANE6+q+d9cbfT0DestqEUzscsfnPBS8pA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=turr9DFjG6k9VqT13NQGFj4Png9YC4FrX8vv2Z8A3mPsbeQctWy1+O1LQjmtxB0Q2 3XHJLA3FiVVYXV+0HqgvDwaB+cQAX1moGW9Mv4GAqRA58hFAoG+pLGQxxIp9HH4Sh0 n7nYHrgTaqfCoqL4VG7Lh0N5GP37UJyXyNhv88oLK08dEkH1npub99oMkanTRFBUz0 T2+ZDFTr6rvqBrr3DiRSYdnhHBFBFc+9ckpgWbew7IrOIDttyxqV0+iJqj+bTXJ3p9 Ak6+EIADj7rCGmW5FGbj/rwEyR1njUg+p2dsbjlVPzqz6DLOBf7w9oV2pigt+Zd6hS jDCRlCkVvx98w== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, arm@kernel.org, Andy Shevchenko , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 20/25] irqchip/armada-370-xp: Use consistent variable names for hwirqs Date: Mon, 1 Jul 2024 19:02:44 +0200 Message-ID: <20240701170249.8128-21-kabel@kernel.org> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240701170249.8128-1-kabel@kernel.org> References: <20240701170249.8128-1-kabel@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240701_100351_466251_7957BB58 X-CRM114-Status: GOOD ( 19.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Use consistent variable names for hwirqs: when iterating, use i, otherwise use hwirq. Signed-off-by: Marek Behún Reviewed-by: Andrew Lunn --- drivers/irqchip/irq-armada-370-xp.c | 52 ++++++++++++++--------------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c index f773d88ead73..b08f49516bee 100644 --- a/drivers/irqchip/irq-armada-370-xp.c +++ b/drivers/irqchip/irq-armada-370-xp.c @@ -117,7 +117,7 @@ #define MPIC_SW_TRIG_INT 0x04 #define MPIC_INT_SET_ENABLE 0x30 #define MPIC_INT_CLEAR_ENABLE 0x34 -#define MPIC_INT_SOURCE_CTL(irq) (0x100 + (irq) * 4) +#define MPIC_INT_SOURCE_CTL(hwirq) (0x100 + (hwirq) * 4) #define MPIC_INT_SOURCE_CPU_MASK GENMASK(3, 0) #define MPIC_INT_IRQ_FIQ_MASK(cpuid) ((BIT(0) | BIT(8)) << (cpuid)) @@ -199,9 +199,9 @@ static inline unsigned int msi_doorbell_end(void) PCI_MSI_FULL_DOORBELL_END; } -static inline bool mpic_is_percpu_irq(irq_hw_number_t irq) +static inline bool mpic_is_percpu_irq(irq_hw_number_t hwirq) { - return irq <= MPIC_MAX_PER_CPU_IRQS; + return hwirq <= MPIC_MAX_PER_CPU_IRQS; } /* @@ -577,20 +577,20 @@ static struct irq_chip mpic_irq_chip = { }; static int mpic_irq_map(struct irq_domain *h, unsigned int virq, - irq_hw_number_t hw) + irq_hw_number_t hwirq) { /* IRQs 0 and 1 cannot be mapped, they are handled internally */ - if (hw <= 1) + if (hwirq <= 1) return -EINVAL; mpic_irq_mask(irq_get_irq_data(virq)); - if (!mpic_is_percpu_irq(hw)) - writel(hw, per_cpu_int_base + MPIC_INT_CLEAR_MASK); + if (!mpic_is_percpu_irq(hwirq)) + writel(hwirq, per_cpu_int_base + MPIC_INT_CLEAR_MASK); else - writel(hw, main_int_base + MPIC_INT_SET_ENABLE); + writel(hwirq, main_int_base + MPIC_INT_SET_ENABLE); irq_set_status_flags(virq, IRQ_LEVEL); - if (mpic_is_percpu_irq(hw)) { + if (mpic_is_percpu_irq(hwirq)) { irq_set_percpu_devid(virq); irq_set_chip_and_handler(virq, &mpic_irq_chip, handle_percpu_devid_irq); @@ -629,15 +629,15 @@ static void mpic_handle_cascade_irq(struct irq_desc *desc) { struct irq_chip *chip = irq_desc_get_chip(desc); unsigned long irqmap, irqsrc, cpuid; - irq_hw_number_t irqn; + irq_hw_number_t hwirq; chained_irq_enter(chip, desc); irqmap = readl_relaxed(per_cpu_int_base + MPIC_PPI_CAUSE); cpuid = cpu_logical_map(smp_processor_id()); - for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) { - irqsrc = readl_relaxed(main_int_base + MPIC_INT_SOURCE_CTL(irqn)); + for_each_set_bit(hwirq, &irqmap, BITS_PER_LONG) { + irqsrc = readl_relaxed(main_int_base + MPIC_INT_SOURCE_CTL(hwirq)); /* Check if the interrupt is not masked on current CPU. * Test IRQ (0-1) and FIQ (8-9) mask bits. @@ -645,12 +645,12 @@ static void mpic_handle_cascade_irq(struct irq_desc *desc) if (!(irqsrc & MPIC_INT_IRQ_FIQ_MASK(cpuid))) continue; - if (irqn == 0 || irqn == 1) { + if (hwirq == 0 || hwirq == 1) { mpic_handle_msi_irq(NULL, true); continue; } - generic_handle_domain_irq(mpic_domain, irqn); + generic_handle_domain_irq(mpic_domain, hwirq); } chained_irq_exit(chip, desc); @@ -658,28 +658,28 @@ static void mpic_handle_cascade_irq(struct irq_desc *desc) static void __exception_irq_entry mpic_handle_irq(struct pt_regs *regs) { - irq_hw_number_t irqnr; + irq_hw_number_t hwirq; u32 irqstat; do { irqstat = readl_relaxed(per_cpu_int_base + MPIC_CPU_INTACK); - irqnr = FIELD_GET(MPIC_CPU_INTACK_IID_MASK, irqstat); + hwirq = FIELD_GET(MPIC_CPU_INTACK_IID_MASK, irqstat); - if (irqnr > 1022) + if (hwirq > 1022) break; - if (irqnr > 1) { - generic_handle_domain_irq(mpic_domain, irqnr); + if (hwirq > 1) { + generic_handle_domain_irq(mpic_domain, hwirq); continue; } /* MSI handling */ - if (irqnr == 1) + if (hwirq == 1) mpic_handle_msi_irq(regs, false); #ifdef CONFIG_SMP /* IPI Handling */ - if (irqnr == 0) { + if (hwirq == 0) { unsigned long ipimask; irq_hw_number_t ipi; @@ -706,24 +706,24 @@ static void mpic_resume(void) bool src0, src1; /* Re-enable interrupts */ - for (irq_hw_number_t irq = 0; irq < mpic_domain->hwirq_max; irq++) { + for (irq_hw_number_t i = 0; i < mpic_domain->hwirq_max; i++) { struct irq_data *data; int virq; - virq = irq_linear_revmap(mpic_domain, irq); + virq = irq_linear_revmap(mpic_domain, i); if (!virq) continue; data = irq_get_irq_data(virq); - if (!mpic_is_percpu_irq(irq)) { + if (!mpic_is_percpu_irq(i)) { /* Non per-CPU interrupts */ - writel(irq, per_cpu_int_base + MPIC_INT_CLEAR_MASK); + writel(i, per_cpu_int_base + MPIC_INT_CLEAR_MASK); if (!irqd_irq_disabled(data)) mpic_irq_unmask(data); } else { /* Per-CPU interrupts */ - writel(irq, main_int_base + MPIC_INT_SET_ENABLE); + writel(i, main_int_base + MPIC_INT_SET_ENABLE); /* * Re-enable on the current CPU, mpic_reenable_percpu()