From patchwork Mon Jul 1 17:02:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 13718448 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5081EC2BD09 for ; Mon, 1 Jul 2024 17:04:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc: To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=bme04NdSjJkB+QLJira4FCBcBR4Fcvv/KFpOsyxJpM8=; b=MzfdFORJCXP58TE+5kOBpCE+Xo NBzW41aC1V/aV/42kMXricYlFLpaCyJB0LimtaHts+9qffNv8nkFfqqSxq2I0/SPAb7Fj+DPp0U2i hFVjjCQBYdYp4Lzn4m5yK1cs2dYbLIn5smaPNByrPRCPJ2ncnWpwLlBKxecXI3SAF8LCCAKdx4TtL PeoGf42zcfR4fFTBAPG6Zi8Mwqaj0TU11UUKxu1Txxze/m96Czy5X9k1DZiWlFwn7n7xpM66nQX4K psazxpsAIhM+MkTGG5sISjVyLQ5ujqU8UDGVIlSHZ2YXart0tr5xZimJ7heD8SKwPvDUUC2F9PEhP zUguspDQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sOKRQ-00000004Dgl-3iQO; Mon, 01 Jul 2024 17:03:48 +0000 Received: from sin.source.kernel.org ([145.40.73.55]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sOKQp-00000004DQ3-09ES for linux-arm-kernel@lists.infradead.org; Mon, 01 Jul 2024 17:03:12 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id 208ECCE1A4D; Mon, 1 Jul 2024 17:03:09 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8DB3AC116B1; Mon, 1 Jul 2024 17:03:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1719853387; bh=2n2BhTjNmb+UssKrDjy/JNqKAJ9FK+ZS58BeHlVSlt0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tbMAITyoebiB0v+VLmq8BNaqQeAOXs9F4Dfd7kQd5Hr2zHVPN+iEN7MC9iql6mQPk U7QGknNxYAOXgM9sgj14YLsQnNEsNpOfkpOIh4YQzMB1BPkOnlfmKivB61yXghdUES R88OFPhr2rt6NSvgvIGFOdyT+JDMuhhcfzJcWPN50e9YSvxvFENRWpKCZhNu/OhoeO 8zFBzF5s9LzVWS4JRtnlMIYvZS52GcmkCaMt/ci1p9ziNHGpvX79fMRy6huuuI4vD/ Yf5+wdKs7LrH+Uu2UisBCwUB+DsFX4+ZDFRmRfuJomNMs2ieD/d5+OhroliLiLHgRB hap2h6rhLEvqQ== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, arm@kernel.org, Andy Shevchenko , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 05/25] irqchip/armada-370-xp: Cosmetic fix parentheses in register constant definitions Date: Mon, 1 Jul 2024 19:02:29 +0200 Message-ID: <20240701170249.8128-6-kabel@kernel.org> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240701170249.8128-1-kabel@kernel.org> References: <20240701170249.8128-1-kabel@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240701_100311_467690_82EF1ADF X-CRM114-Status: UNSURE ( 9.44 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Drop parentheses where not needed and add where makes sense in register constant definitions. Signed-off-by: Marek Behún Reviewed-by: Andrew Lunn --- drivers/irqchip/irq-armada-370-xp.c | 38 ++++++++++++++--------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c index 18aca9b5d3b3..14d213e9b0d2 100644 --- a/drivers/irqchip/irq-armada-370-xp.c +++ b/drivers/irqchip/irq-armada-370-xp.c @@ -116,33 +116,33 @@ */ /* Registers relative to main_int_base */ -#define ARMADA_370_XP_INT_CONTROL (0x00) -#define ARMADA_370_XP_SW_TRIG_INT (0x04) -#define ARMADA_370_XP_INT_SET_ENABLE (0x30) -#define ARMADA_370_XP_INT_CLEAR_ENABLE (0x34) -#define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + irq*4) +#define ARMADA_370_XP_INT_CONTROL 0x00 +#define ARMADA_370_XP_SW_TRIG_INT 0x04 +#define ARMADA_370_XP_INT_SET_ENABLE 0x30 +#define ARMADA_370_XP_INT_CLEAR_ENABLE 0x34 +#define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + (irq) * 4) #define ARMADA_370_XP_INT_SOURCE_CPU_MASK GENMASK(3, 0) -#define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid) ((BIT(0) | BIT(8)) << cpuid) +#define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid) ((BIT(0) | BIT(8)) << (cpuid)) /* Registers relative to per_cpu_int_base */ -#define ARMADA_370_XP_IN_DRBEL_CAUSE (0x08) -#define ARMADA_370_XP_IN_DRBEL_MASK (0x0c) -#define ARMADA_375_PPI_CAUSE (0x10) -#define ARMADA_370_XP_CPU_INTACK (0x44) -#define ARMADA_370_XP_INT_SET_MASK (0x48) -#define ARMADA_370_XP_INT_CLEAR_MASK (0x4C) -#define ARMADA_370_XP_INT_FABRIC_MASK (0x54) +#define ARMADA_370_XP_IN_DRBEL_CAUSE 0x08 +#define ARMADA_370_XP_IN_DRBEL_MASK 0x0c +#define ARMADA_375_PPI_CAUSE 0x10 +#define ARMADA_370_XP_CPU_INTACK 0x44 +#define ARMADA_370_XP_INT_SET_MASK 0x48 +#define ARMADA_370_XP_INT_CLEAR_MASK 0x4C +#define ARMADA_370_XP_INT_FABRIC_MASK 0x54 #define ARMADA_370_XP_INT_CAUSE_PERF(cpu) BIT(cpu) -#define ARMADA_370_XP_MAX_PER_CPU_IRQS (28) +#define ARMADA_370_XP_MAX_PER_CPU_IRQS 28 /* IPI and MSI interrupt definitions for IPI platforms */ -#define IPI_DOORBELL_START (0) -#define IPI_DOORBELL_END (8) +#define IPI_DOORBELL_START 0 +#define IPI_DOORBELL_END 8 #define IPI_DOORBELL_MASK GENMASK(7, 0) -#define PCI_MSI_DOORBELL_START (16) -#define PCI_MSI_DOORBELL_NR (16) -#define PCI_MSI_DOORBELL_END (32) +#define PCI_MSI_DOORBELL_START 16 +#define PCI_MSI_DOORBELL_NR 16 +#define PCI_MSI_DOORBELL_END 32 #define PCI_MSI_DOORBELL_MASK GENMASK(31, 16) /* MSI interrupt definitions for non-IPI platforms */