From patchwork Mon Jul 1 17:02:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marek_Beh=C3=BAn?= X-Patchwork-Id: 13718449 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4FE83C3065A for ; Mon, 1 Jul 2024 17:04:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc: To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=FqVKABumcMbUAJl9BNC1ws5IDdkAPFULO/uN8EO/BTk=; b=mYMt8QZvvpVPYAVm9mifNVN7hV ymOoicWDArvgqWjoRwslEI1ZTROVhoB54wuuMMWrQH+/agy+GEYvuBO8+pxLLjcm+X2IndJp4mkmN zGza9EBMAYaxNtkH35kOlPX5M2UtVMC8S/kO0Ws9FNOlpAeokj39h4osOSwpuPaV5i65eInxWdz0M P0wsehW2ubXMxJqqYFiPLu64AS9K5fxIgbBUlo0pEYm2oCJSJ7GhswW3qSnmrP4YmsSEEfxTK6C2m tvHj079cnCdVpbta5TJ86t6PSs7P8ZOrgZV7kroFJ3JrPFtjRPoACSVaWP9RENXDOw5UfzTs6ITaN etF8R1sQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sOKRa-00000004Dmm-3ENg; Mon, 01 Jul 2024 17:03:58 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sOKQp-00000004DQB-1vMK for linux-arm-kernel@lists.infradead.org; Mon, 01 Jul 2024 17:03:12 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id A015C614D1; Mon, 1 Jul 2024 17:03:10 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2D879C4AF10; Mon, 1 Jul 2024 17:03:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1719853390; bh=/nbPhhEVkd+EA06cZxXSNQfFST8DJ6SAHH6xkJn1W6g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dtW5q5SERJoTGlLU69v//F6PGPfSjdCfMkQNtSSkWzKEijKWNHoPZtEBLpmPnJV6T H6XDGpgHkXu48fnzYKJUg38HHGG/YrPsSEnRi1aSpdAZwKaUDbBx0CrZxNjsnVZ6fQ TPfelwsptK3MsYSjDRzaFyj5+Cj1rKjmFVG6ijcIgi06c/DSTMQqdnevvyxbD0LIru b16Jpp2HxU4qQq6j9UEOQ8rqxE5oFdf5J+NANwAsXTy81iSF5VhGrJDD68WYTqpjkX WF6qw55zJ/nb5/lWvrabC62iJX7k70i+JL8j0D8P2FM4PgLU1iX7GAKYtV5ySclhR7 p0QJ/fOduKvpw== From: =?utf-8?q?Marek_Beh=C3=BAn?= To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, arm@kernel.org, Andy Shevchenko , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Cc: =?utf-8?q?Marek_Beh=C3=BAn?= Subject: [PATCH 06/25] irqchip/armada-370-xp: Change register constants prefix to MPIC_ Date: Mon, 1 Jul 2024 19:02:30 +0200 Message-ID: <20240701170249.8128-7-kabel@kernel.org> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240701170249.8128-1-kabel@kernel.org> References: <20240701170249.8128-1-kabel@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240701_100311_668338_F7A41EBA X-CRM114-Status: GOOD ( 24.98 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Change the long ARMADA_370_XP_ prefix in register constants (ARMADA_375_ in one case) to MPIC_. The rationale is that it is shorter and more generic (this controller is called MPIC and is also used on Armada 38x and 39x). Signed-off-by: Marek Behún Reviewed-by: Andrew Lunn --- drivers/irqchip/irq-armada-370-xp.c | 148 +++++++++++++--------------- 1 file changed, 69 insertions(+), 79 deletions(-) diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c index 14d213e9b0d2..8f52de6d8921 100644 --- a/drivers/irqchip/irq-armada-370-xp.c +++ b/drivers/irqchip/irq-armada-370-xp.c @@ -66,18 +66,17 @@ * device * * The "global interrupt mask/unmask" is modified using the - * ARMADA_370_XP_INT_SET_ENABLE and ARMADA_370_XP_INT_CLEAR_ENABLE + * MPIC_INT_SET_ENABLE and MPIC_INT_CLEAR_ENABLE * registers, which are relative to "main_int_base". * - * The "per-CPU mask/unmask" is modified using the - * ARMADA_370_XP_INT_SET_MASK and ARMADA_370_XP_INT_CLEAR_MASK - * registers, which are relative to "per_cpu_int_base". This base - * address points to a special address, which automatically accesses - * the registers of the current CPU. + * The "per-CPU mask/unmask" is modified using the MPIC_INT_SET_MASK + * and MPIC_INT_CLEAR_MASK registers, which are relative to + * "per_cpu_int_base". This base address points to a special address, + * which automatically accesses the registers of the current CPU. * * The per-CPU mask/unmask can also be adjusted using the global - * per-interrupt ARMADA_370_XP_INT_SOURCE_CTL register, which we use - * to configure interrupt affinity. + * per-interrupt MPIC_INT_SOURCE_CTL register, which we use to + * configure interrupt affinity. * * Due to this model, all interrupts need to be mask/unmasked at two * different levels: at the global level and at the per-CPU level. @@ -91,9 +90,8 @@ * the current CPU, running the ->map() code. This allows to have * the interrupt unmasked at this level in non-SMP * configurations. In SMP configurations, the ->set_affinity() - * callback is called, which using the - * ARMADA_370_XP_INT_SOURCE_CTL() readjusts the per-CPU mask/unmask - * for the interrupt. + * callback is called, which using the MPIC_INT_SOURCE_CTL() + * readjusts the per-CPU mask/unmask for the interrupt. * * The ->mask() and ->unmask() operations only mask/unmask the * interrupt at the "global" level. @@ -116,25 +114,25 @@ */ /* Registers relative to main_int_base */ -#define ARMADA_370_XP_INT_CONTROL 0x00 -#define ARMADA_370_XP_SW_TRIG_INT 0x04 -#define ARMADA_370_XP_INT_SET_ENABLE 0x30 -#define ARMADA_370_XP_INT_CLEAR_ENABLE 0x34 -#define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + (irq) * 4) -#define ARMADA_370_XP_INT_SOURCE_CPU_MASK GENMASK(3, 0) -#define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid) ((BIT(0) | BIT(8)) << (cpuid)) +#define MPIC_INT_CONTROL 0x00 +#define MPIC_SW_TRIG_INT 0x04 +#define MPIC_INT_SET_ENABLE 0x30 +#define MPIC_INT_CLEAR_ENABLE 0x34 +#define MPIC_INT_SOURCE_CTL(irq) (0x100 + (irq) * 4) +#define MPIC_INT_SOURCE_CPU_MASK GENMASK(3, 0) +#define MPIC_INT_IRQ_FIQ_MASK(cpuid) ((BIT(0) | BIT(8)) << (cpuid)) /* Registers relative to per_cpu_int_base */ -#define ARMADA_370_XP_IN_DRBEL_CAUSE 0x08 -#define ARMADA_370_XP_IN_DRBEL_MASK 0x0c -#define ARMADA_375_PPI_CAUSE 0x10 -#define ARMADA_370_XP_CPU_INTACK 0x44 -#define ARMADA_370_XP_INT_SET_MASK 0x48 -#define ARMADA_370_XP_INT_CLEAR_MASK 0x4C -#define ARMADA_370_XP_INT_FABRIC_MASK 0x54 -#define ARMADA_370_XP_INT_CAUSE_PERF(cpu) BIT(cpu) +#define MPIC_IN_DRBEL_CAUSE 0x08 +#define MPIC_IN_DRBEL_MASK 0x0c +#define MPIC_PPI_CAUSE 0x10 +#define MPIC_CPU_INTACK 0x44 +#define MPIC_INT_SET_MASK 0x48 +#define MPIC_INT_CLEAR_MASK 0x4C +#define MPIC_INT_FABRIC_MASK 0x54 +#define MPIC_INT_CAUSE_PERF(cpu) BIT(cpu) -#define ARMADA_370_XP_MAX_PER_CPU_IRQS 28 +#define MPIC_MAX_PER_CPU_IRQS 28 /* IPI and MSI interrupt definitions for IPI platforms */ #define IPI_DOORBELL_START 0 @@ -203,7 +201,7 @@ static inline unsigned int msi_doorbell_end(void) static inline bool is_percpu_irq(irq_hw_number_t irq) { - if (irq <= ARMADA_370_XP_MAX_PER_CPU_IRQS) + if (irq <= MPIC_MAX_PER_CPU_IRQS) return true; return false; @@ -219,9 +217,9 @@ static void armada_370_xp_irq_mask(struct irq_data *d) irq_hw_number_t hwirq = irqd_to_hwirq(d); if (!is_percpu_irq(hwirq)) - writel(hwirq, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE); + writel(hwirq, main_int_base + MPIC_INT_CLEAR_ENABLE); else - writel(hwirq, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK); + writel(hwirq, per_cpu_int_base + MPIC_INT_SET_MASK); } static void armada_370_xp_irq_unmask(struct irq_data *d) @@ -229,9 +227,9 @@ static void armada_370_xp_irq_unmask(struct irq_data *d) irq_hw_number_t hwirq = irqd_to_hwirq(d); if (!is_percpu_irq(hwirq)) - writel(hwirq, main_int_base + ARMADA_370_XP_INT_SET_ENABLE); + writel(hwirq, main_int_base + MPIC_INT_SET_ENABLE); else - writel(hwirq, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK); + writel(hwirq, per_cpu_int_base + MPIC_INT_CLEAR_MASK); } #ifdef CONFIG_PCI_MSI @@ -324,18 +322,18 @@ static void armada_370_xp_msi_reenable_percpu(void) u32 reg; /* Enable MSI doorbell mask and combined cpu local interrupt */ - reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK); + reg = readl(per_cpu_int_base + MPIC_IN_DRBEL_MASK); reg |= msi_doorbell_mask(); - writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK); + writel(reg, per_cpu_int_base + MPIC_IN_DRBEL_MASK); /* Unmask local doorbell interrupt */ - writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK); + writel(1, per_cpu_int_base + MPIC_INT_CLEAR_MASK); } static int armada_370_xp_msi_init(struct device_node *node, phys_addr_t main_int_phys_base) { - msi_doorbell_addr = main_int_phys_base + ARMADA_370_XP_SW_TRIG_INT; + msi_doorbell_addr = main_int_phys_base + MPIC_SW_TRIG_INT; armada_370_xp_msi_inner_domain = irq_domain_add_linear(NULL, msi_doorbell_size(), @@ -356,7 +354,7 @@ static int armada_370_xp_msi_init(struct device_node *node, /* Unmask low 16 MSI irqs on non-IPI platforms */ if (!is_ipi_available()) - writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK); + writel(0, per_cpu_int_base + MPIC_INT_CLEAR_MASK); return 0; } @@ -384,8 +382,8 @@ static void armada_xp_mpic_perf_init(void) cpuid = cpu_logical_map(smp_processor_id()); /* Enable Performance Counter Overflow interrupts */ - writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid), - per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK); + writel(MPIC_INT_CAUSE_PERF(cpuid), + per_cpu_int_base + MPIC_INT_FABRIC_MASK); } #ifdef CONFIG_SMP @@ -394,17 +392,17 @@ static struct irq_domain *ipi_domain; static void armada_370_xp_ipi_mask(struct irq_data *d) { u32 reg; - reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK); + reg = readl(per_cpu_int_base + MPIC_IN_DRBEL_MASK); reg &= ~BIT(d->hwirq); - writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK); + writel(reg, per_cpu_int_base + MPIC_IN_DRBEL_MASK); } static void armada_370_xp_ipi_unmask(struct irq_data *d) { u32 reg; - reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK); + reg = readl(per_cpu_int_base + MPIC_IN_DRBEL_MASK); reg |= BIT(d->hwirq); - writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK); + writel(reg, per_cpu_int_base + MPIC_IN_DRBEL_MASK); } static void armada_370_xp_ipi_send_mask(struct irq_data *d, @@ -424,13 +422,12 @@ static void armada_370_xp_ipi_send_mask(struct irq_data *d, dsb(); /* submit softirq */ - writel((map << 8) | d->hwirq, main_int_base + - ARMADA_370_XP_SW_TRIG_INT); + writel((map << 8) | d->hwirq, main_int_base + MPIC_SW_TRIG_INT); } static void armada_370_xp_ipi_ack(struct irq_data *d) { - writel(~BIT(d->hwirq), per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE); + writel(~BIT(d->hwirq), per_cpu_int_base + MPIC_IN_DRBEL_CAUSE); } static struct irq_chip ipi_irqchip = { @@ -515,9 +512,8 @@ static int armada_xp_set_affinity(struct irq_data *d, /* Select a single core from the affinity mask which is online */ cpu = cpumask_any_and(mask_val, cpu_online_mask); - atomic_io_modify(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq), - ARMADA_370_XP_INT_SOURCE_CPU_MASK, - BIT(cpu_logical_map(cpu))); + atomic_io_modify(main_int_base + MPIC_INT_SOURCE_CTL(hwirq), + MPIC_INT_SOURCE_CPU_MASK, BIT(cpu_logical_map(cpu))); irq_data_update_effective_affinity(d, cpumask_of(cpu)); @@ -529,23 +525,23 @@ static void armada_xp_mpic_smp_cpu_init(void) u32 control; int nr_irqs, i; - control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL); + control = readl(main_int_base + MPIC_INT_CONTROL); nr_irqs = (control >> 2) & 0x3ff; for (i = 0; i < nr_irqs; i++) - writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK); + writel(i, per_cpu_int_base + MPIC_INT_SET_MASK); if (!is_ipi_available()) return; /* Disable all IPIs */ - writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK); + writel(0, per_cpu_int_base + MPIC_IN_DRBEL_MASK); /* Clear pending IPIs */ - writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE); + writel(0, per_cpu_int_base + MPIC_IN_DRBEL_CAUSE); /* Unmask IPI interrupt */ - writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK); + writel(0, per_cpu_int_base + MPIC_INT_CLEAR_MASK); } static void armada_xp_mpic_reenable_percpu(void) @@ -553,7 +549,7 @@ static void armada_xp_mpic_reenable_percpu(void) unsigned int irq; /* Re-enable per-CPU interrupts that were enabled before suspend */ - for (irq = 0; irq < ARMADA_370_XP_MAX_PER_CPU_IRQS; irq++) { + for (irq = 0; irq < MPIC_MAX_PER_CPU_IRQS; irq++) { struct irq_data *data; int virq; @@ -615,10 +611,9 @@ static int armada_370_xp_mpic_irq_map(struct irq_domain *h, armada_370_xp_irq_mask(irq_get_irq_data(virq)); if (!is_percpu_irq(hw)) - writel(hw, per_cpu_int_base + - ARMADA_370_XP_INT_CLEAR_MASK); + writel(hw, per_cpu_int_base + MPIC_INT_CLEAR_MASK); else - writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE); + writel(hw, main_int_base + MPIC_INT_SET_ENABLE); irq_set_status_flags(virq, IRQ_LEVEL); if (is_percpu_irq(hw)) { @@ -645,10 +640,10 @@ static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained) { u32 msimask, msinr; - msimask = readl_relaxed(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE); + msimask = readl_relaxed(per_cpu_int_base + MPIC_IN_DRBEL_CAUSE); msimask &= msi_doorbell_mask(); - writel(~msimask, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE); + writel(~msimask, per_cpu_int_base + MPIC_IN_DRBEL_CAUSE); for (msinr = msi_doorbell_start(); msinr < msi_doorbell_end(); msinr++) { @@ -673,17 +668,16 @@ static void armada_370_xp_mpic_handle_cascade_irq(struct irq_desc *desc) chained_irq_enter(chip, desc); - irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE); + irqmap = readl_relaxed(per_cpu_int_base + MPIC_PPI_CAUSE); cpuid = cpu_logical_map(smp_processor_id()); for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) { - irqsrc = readl_relaxed(main_int_base + - ARMADA_370_XP_INT_SOURCE_CTL(irqn)); + irqsrc = readl_relaxed(main_int_base + MPIC_INT_SOURCE_CTL(irqn)); /* Check if the interrupt is not masked on current CPU. * Test IRQ (0-1) and FIQ (8-9) mask bits. */ - if (!(irqsrc & ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid))) + if (!(irqsrc & MPIC_INT_IRQ_FIQ_MASK(cpuid))) continue; if (irqn == 0 || irqn == 1) { @@ -703,8 +697,7 @@ armada_370_xp_handle_irq(struct pt_regs *regs) u32 irqstat, irqnr; do { - irqstat = readl_relaxed(per_cpu_int_base + - ARMADA_370_XP_CPU_INTACK); + irqstat = readl_relaxed(per_cpu_int_base + MPIC_CPU_INTACK); irqnr = irqstat & 0x3FF; if (irqnr > 1022) @@ -727,7 +720,7 @@ armada_370_xp_handle_irq(struct pt_regs *regs) int ipi; ipimask = readl_relaxed(per_cpu_int_base + - ARMADA_370_XP_IN_DRBEL_CAUSE) + MPIC_IN_DRBEL_CAUSE) & IPI_DOORBELL_MASK; for_each_set_bit(ipi, &ipimask, IPI_DOORBELL_END) @@ -740,7 +733,7 @@ armada_370_xp_handle_irq(struct pt_regs *regs) static int armada_370_xp_mpic_suspend(void) { - doorbell_mask_reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK); + doorbell_mask_reg = readl(per_cpu_int_base + MPIC_IN_DRBEL_MASK); return 0; } @@ -751,7 +744,7 @@ static void armada_370_xp_mpic_resume(void) irq_hw_number_t irq; /* Re-enable interrupts */ - nirqs = (readl(main_int_base + ARMADA_370_XP_INT_CONTROL) >> 2) & 0x3ff; + nirqs = (readl(main_int_base + MPIC_INT_CONTROL) >> 2) & 0x3ff; for (irq = 0; irq < nirqs; irq++) { struct irq_data *data; int virq; @@ -764,14 +757,12 @@ static void armada_370_xp_mpic_resume(void) if (!is_percpu_irq(irq)) { /* Non per-CPU interrupts */ - writel(irq, per_cpu_int_base + - ARMADA_370_XP_INT_CLEAR_MASK); + writel(irq, per_cpu_int_base + MPIC_INT_CLEAR_MASK); if (!irqd_irq_disabled(data)) armada_370_xp_irq_unmask(data); } else { /* Per-CPU interrupts */ - writel(irq, main_int_base + - ARMADA_370_XP_INT_SET_ENABLE); + writel(irq, main_int_base + MPIC_INT_SET_ENABLE); /* * Re-enable on the current CPU, @@ -784,8 +775,7 @@ static void armada_370_xp_mpic_resume(void) } /* Reconfigure doorbells for IPIs and MSIs */ - writel(doorbell_mask_reg, - per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MASK); + writel(doorbell_mask_reg, per_cpu_int_base + MPIC_IN_DRBEL_MASK); if (is_ipi_available()) { src0 = doorbell_mask_reg & IPI_DOORBELL_MASK; @@ -796,9 +786,9 @@ static void armada_370_xp_mpic_resume(void) } if (src0) - writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK); + writel(0, per_cpu_int_base + MPIC_INT_CLEAR_MASK); if (src1) - writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK); + writel(1, per_cpu_int_base + MPIC_INT_CLEAR_MASK); if (is_ipi_available()) ipi_resume(); @@ -834,11 +824,11 @@ static int __init armada_370_xp_mpic_of_init(struct device_node *node, resource_size(&per_cpu_int_res)); BUG_ON(!per_cpu_int_base); - control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL); + control = readl(main_int_base + MPIC_INT_CONTROL); nr_irqs = (control >> 2) & 0x3ff; for (i = 0; i < nr_irqs; i++) - writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE); + writel(i, main_int_base + MPIC_INT_CLEAR_ENABLE); armada_370_xp_mpic_domain = irq_domain_add_linear(node, nr_irqs,