Message ID | 20240703102821.196112-1-varshini.rajendran@microchip.com (mailing list archive) |
---|---|
State | New |
Headers | show
Return-Path: <linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org> X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BB3E5C2BD09 for <linux-arm-kernel@archiver.kernel.org>; Wed, 3 Jul 2024 10:30:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=91HNxeq2wu1ge47j25ejP8jOTotS1cgYabJgCU/RZOQ=; b=T1QJvSRuw894GRuRU+1j3Wh/Fd 6oYyGEQwCB+eSFE7yCT0CdlJli3FZcNdqTKtRo4PFMWp6q4PLwnVAXPXmotnNfyUSJ6O9y33U69UG UywWl+e7A6oNkanVT4lkWcbDEBGU81i9/eCpUUvRAOXpGiAa0CqBPLhkR9KoUEwCBdTfYRQYvWXhL sd60Xs3//T+b70OblQPyyfXTodYQjqwiAy14jkpDEWO0v54jh2tcN8/6+ZDm42rSWRaWTNGBsIrs+ 84mENM5bVOsDrPjaRqct4pJxJsYzV2rqXrA1enRshbsXpJQJidZLkP+RkWdacBF3TIPRmQ0frQL1h 8ULjhhMQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sOxFX-00000009m8G-3Vrp; Wed, 03 Jul 2024 10:30:08 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sOxEE-00000009lTj-1QFN for linux-arm-kernel@lists.infradead.org; Wed, 03 Jul 2024 10:28:48 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1720002527; x=1751538527; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XD4Q7cZLicWEz0JXcKOPLuwfCe9wBLZj9EmkWqD4OZA=; b=u0dJ5i4p8XG+fWIOUjdio20VhQEDvSge1zInwGxZmuoBTbGV2qggMnTY rVGTtlIU6O+Isc2LcjJ7jprxLE3wR/HGjNHNKBCMMfc11rluJ3vdVCJqY DBm4gkcrGKnlXMbAxpZ3/IQJpfS1k7AXwcJco9TNBLi9oW3J7WriSsmMA NzzdB1KRFuJOrHA/qGoFkiPV/1yXEZmOKATYrn57tO6dEroiExPf0Wzym qDrmT+iGdONsZc+1SvhzPbCNObLWkVPdmGK7qvUhdnpAyAYUY5dYjWuVO SQoSYdSqKA+KpA/Qp+Exqf9HwxhIBm6uLLybmBxzEAyxHrvjK0qdKDZbF Q==; X-CSE-ConnectionGUID: ywlN1IFORca1IOesWlMguw== X-CSE-MsgGUID: PL6zp7yMQlaYofmNGkNlPA== X-IronPort-AV: E=Sophos;i="6.09,181,1716274800"; d="scan'208";a="28804768" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 03 Jul 2024 03:28:45 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 3 Jul 2024 03:28:28 -0700 Received: from che-lt-i67070.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 3 Jul 2024 03:28:25 -0700 From: Varshini Rajendran <varshini.rajendran@microchip.com> To: <tglx@linutronix.de>, <nicolas.ferre@microchip.com>, <alexandre.belloni@bootlin.com>, <claudiu.beznea@tuxon.dev>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org> CC: <varshini.rajendran@microchip.com> Subject: [PATCH v5 16/27] irqchip/atmel-aic5: Add support to get nr_irqs from DT for sam9x60 & sam9x7 Date: Wed, 3 Jul 2024 15:58:21 +0530 Message-ID: <20240703102821.196112-1-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240703102011.193343-1-varshini.rajendran@microchip.com> References: <20240703102011.193343-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240703_032846_469068_3FEDBC05 X-CRM114-Status: GOOD ( 13.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: <linux-arm-kernel.lists.infradead.org> List-Unsubscribe: <http://lists.infradead.org/mailman/options/linux-arm-kernel>, <mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe> List-Archive: <http://lists.infradead.org/pipermail/linux-arm-kernel/> List-Post: <mailto:linux-arm-kernel@lists.infradead.org> List-Help: <mailto:linux-arm-kernel-request@lists.infradead.org?subject=help> List-Subscribe: <http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>, <mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe> Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org> Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org |
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Add support for sam9x7 SoC family
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expand
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diff --git a/drivers/irqchip/irq-atmel-aic5.c b/drivers/irqchip/irq-atmel-aic5.c index 145535bd7560..164b5a9b0f9b 100644 --- a/drivers/irqchip/irq-atmel-aic5.c +++ b/drivers/irqchip/irq-atmel-aic5.c @@ -403,6 +403,12 @@ IRQCHIP_DECLARE(sama5d4_aic5, "atmel,sama5d4-aic", sama5d4_aic5_of_init); static int __init sam9x60_aic5_of_init(struct device_node *node, struct device_node *parent) { - return aic5_of_init(node, parent, NR_SAM9X60_IRQS); + int ret, nr_irqs; + + ret = of_property_read_u32(node, "microchip,nr-irqs", &nr_irqs); + if (ret) + return aic5_of_init(node, parent, NR_SAM9X60_IRQS); + + return aic5_of_init(node, parent, nr_irqs); } IRQCHIP_DECLARE(sam9x60_aic5, "microchip,sam9x60-aic", sam9x60_aic5_of_init);
Add support to get number of IRQs from the respective DT node for sam9x60 and sam9x7 devices. Since only this factor differs between the two SoCs, this patch adds support for the same. The macro is still used as a fallback for the sake of old sam9x60 DTs to work so that there is no ABI breakage. The property is a enforced as a requirement for sam9x7 alone. Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com> --- Changes in v5: - Changed the ABI breaking code. - Added sam9x60 NR_IRQ as fallback for older DTS to work. --- drivers/irqchip/irq-atmel-aic5.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)