| Message ID | 20240704135653.2969532-1-ciprianmarian.costea@oss.nxp.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [v2] arm64: dts: s32g: Disable usdhc write-protect | expand |
On 04/07/2024 15:56, Ciprian Costea wrote: > NXP S32G2/S32G3 SoC based platforms do not > use a pin for SD-Card write protection used by > the uSDHC controller. > > Hence, adding 'disable-wp' usdhc device-tree property in order to fix > observed warnings on SD boot as the following: > "host does not support reading read-only switch, assuming write-enable" > > Signed-off-by: Ciprian Costea <ciprianmarian.costea@oss.nxp.com> Reviewed-by: Matthias Brugger <mbrugger@suse.com> > --- > arch/arm64/boot/dts/freescale/s32g274a-evb.dts | 1 + > arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts | 1 + > arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts | 3 ++- > 3 files changed, 4 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts > index 00070c949e2a..dbe498798bd9 100644 > --- a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts > +++ b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts > @@ -34,5 +34,6 @@ &uart0 { > }; > > &usdhc0 { > + disable-wp; > status = "okay"; > }; > diff --git a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts > index b3fc12899cae..ab1e5caaeae7 100644 > --- a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts > +++ b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts > @@ -40,5 +40,6 @@ &uart1 { > }; > > &usdhc0 { > + disable-wp; > status = "okay"; > }; > diff --git a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts > index 9d674819876e..176e5af191c8 100644 > --- a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts > +++ b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts > @@ -1,6 +1,6 @@ > // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) > /* > - * Copyright 2021-2023 NXP > + * Copyright 2021-2024 NXP > * > * NXP S32G3 Reference Design Board 3 (S32G-VNP-RDB3) > */ > @@ -41,5 +41,6 @@ &uart1 { > > &usdhc0 { > bus-width = <8>; > + disable-wp; > status = "okay"; > };
diff --git a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts index 00070c949e2a..dbe498798bd9 100644 --- a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts +++ b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts @@ -34,5 +34,6 @@ &uart0 { }; &usdhc0 { + disable-wp; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts index b3fc12899cae..ab1e5caaeae7 100644 --- a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts +++ b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts @@ -40,5 +40,6 @@ &uart1 { }; &usdhc0 { + disable-wp; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts index 9d674819876e..176e5af191c8 100644 --- a/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts +++ b/arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright 2021-2023 NXP + * Copyright 2021-2024 NXP * * NXP S32G3 Reference Design Board 3 (S32G-VNP-RDB3) */ @@ -41,5 +41,6 @@ &uart1 { &usdhc0 { bus-width = <8>; + disable-wp; status = "okay"; };
NXP S32G2/S32G3 SoC based platforms do not use a pin for SD-Card write protection used by the uSDHC controller. Hence, adding 'disable-wp' usdhc device-tree property in order to fix observed warnings on SD boot as the following: "host does not support reading read-only switch, assuming write-enable" Signed-off-by: Ciprian Costea <ciprianmarian.costea@oss.nxp.com> --- arch/arm64/boot/dts/freescale/s32g274a-evb.dts | 1 + arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts | 1 + arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts | 3 ++- 3 files changed, 4 insertions(+), 1 deletion(-)