diff mbox series

[03/10] dt-bindings: display: imx: Add i.MX8qxp Display Controller pixel engine

Message ID 20240705090932.1880496-4-victor.liu@nxp.com (mailing list archive)
State New
Headers show
Series Add Freescale i.MX8qxp Display Controller support | expand

Commit Message

Liu Ying July 5, 2024, 9:09 a.m. UTC 
i.MX8qxp Display Controller pixel engine consists of all processing units
that operate in the AXI bus clock domain.  Command sequencer and interrupt
controller of the Display Controller work with AXI bus clock, but they are
not in pixel engine.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
---
 .../imx/fsl,imx8qxp-dc-pixel-engine.yaml      | 264 ++++++++++++++++++
 1 file changed, 264 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-pixel-engine.yaml

Comments

Krzysztof Kozlowski July 7, 2024, 2:02 p.m. UTC | #1 
On 05/07/2024 11:09, Liu Ying wrote:
> i.MX8qxp Display Controller pixel engine consists of all processing units
> that operate in the AXI bus clock domain.  Command sequencer and interrupt
> controller of the Display Controller work with AXI bus clock, but they are
> not in pixel engine.
> 
> Signed-off-by: Liu Ying <victor.liu@nxp.com>
> ---


> +
> +        extdst@56180a40 {
> +            compatible = "fsl,imx8qxp-dc-extdst";
> +            reg = <0x56180a40 0x7>, <0x56186000 0x400>;
> +            reg-names = "pec", "cfg";
> +            interrupt-parent = <&dc0_intc>;
> +            interrupts = <12>, <13>, <14>;
> +            interrupt-names = "shdload", "framecomplete", "seqcomplete";
> +            fsl,dc-ed-id = <5>;
> +        };
> +
> +        fetchwarp@56180a60 {
> +            compatible = "fsl,imx8qxp-dc-fetchwarp";
> +            reg = <0x56180a60 0x4>, <0x56186400 0x400>;

Aha, one word for address range.

Sorry, these are not separate devices.

Best regards,
Krzysztof
Liu Ying July 8, 2024, 6:47 a.m. UTC | #2 
On 07/07/2024, Krzysztof Kozlowski wrote:
> On 05/07/2024 11:09, Liu Ying wrote:
>> i.MX8qxp Display Controller pixel engine consists of all processing units
>> that operate in the AXI bus clock domain.  Command sequencer and interrupt
>> controller of the Display Controller work with AXI bus clock, but they are
>> not in pixel engine.
>>
>> Signed-off-by: Liu Ying <victor.liu@nxp.com>
>> ---
> 
> 
>> +
>> +        extdst@56180a40 {
>> +            compatible = "fsl,imx8qxp-dc-extdst";
>> +            reg = <0x56180a40 0x7>, <0x56186000 0x400>;
>> +            reg-names = "pec", "cfg";
>> +            interrupt-parent = <&dc0_intc>;
>> +            interrupts = <12>, <13>, <14>;
>> +            interrupt-names = "shdload", "framecomplete", "seqcomplete";
>> +            fsl,dc-ed-id = <5>;
>> +        };
>> +
>> +        fetchwarp@56180a60 {
>> +            compatible = "fsl,imx8qxp-dc-fetchwarp";
>> +            reg = <0x56180a60 0x4>, <0x56186400 0x400>;
> 
> Aha, one word for address range.

Sorry, I don't get your idea here.

> 
> Sorry, these are not separate devices.

Hmm, again, Maxime suggested to use separate devices.

> 
> Best regards,
> Krzysztof
> 
>
Krzysztof Kozlowski July 8, 2024, 2:05 p.m. UTC | #3 
On 08/07/2024 08:47, Liu Ying wrote:
> On 07/07/2024, Krzysztof Kozlowski wrote:
>> On 05/07/2024 11:09, Liu Ying wrote:
>>> i.MX8qxp Display Controller pixel engine consists of all processing units
>>> that operate in the AXI bus clock domain.  Command sequencer and interrupt
>>> controller of the Display Controller work with AXI bus clock, but they are
>>> not in pixel engine.
>>>
>>> Signed-off-by: Liu Ying <victor.liu@nxp.com>
>>> ---
>>
>>
>>> +
>>> +        extdst@56180a40 {
>>> +            compatible = "fsl,imx8qxp-dc-extdst";
>>> +            reg = <0x56180a40 0x7>, <0x56186000 0x400>;
>>> +            reg-names = "pec", "cfg";
>>> +            interrupt-parent = <&dc0_intc>;
>>> +            interrupts = <12>, <13>, <14>;
>>> +            interrupt-names = "shdload", "framecomplete", "seqcomplete";
>>> +            fsl,dc-ed-id = <5>;
>>> +        };
>>> +
>>> +        fetchwarp@56180a60 {
>>> +            compatible = "fsl,imx8qxp-dc-fetchwarp";
>>> +            reg = <0x56180a60 0x4>, <0x56186400 0x400>;
>>
>> Aha, one word for address range.
> 
> Sorry, I don't get your idea here.

How many words are in the first IO address range?

One.

That is not a separate device.

> 
>>
>> Sorry, these are not separate devices.
> 
> Hmm, again, Maxime suggested to use separate devices.

To some level you can create separate devices, but for one register?

Best regards,
Krzysztof
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-pixel-engine.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-pixel-engine.yaml
new file mode 100644
index 000000000000..29dd7bac6f7f
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-pixel-engine.yaml
@@ -0,0 +1,264 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-pixel-engine.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qxp Display Controller Pixel Engine
+
+description:
+  All Processing Units that operate in the AXI bus clock domain. Pixel
+  pipelines have the ability to stall when a destination is busy. Implements
+  all communication to memory resources and most of the image processing
+  functions. Interconnection of Processing Units is re-configurable.
+
+maintainers:
+  - Liu Ying <victor.liu@nxp.com>
+
+properties:
+  compatible:
+    const: fsl,imx8qxp-dc-pixel-engine
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 1
+
+  ranges: true
+
+patternProperties:
+  "^blit-engine@[0-9a-f]+$":
+    type: object
+    additionalProperties: true
+
+    properties:
+      compatible:
+        const: fsl,imx8qxp-dc-blit-engine
+
+  "^constframe@[0-9a-f]+$":
+    type: object
+    additionalProperties: true
+
+    properties:
+      compatible:
+        const: fsl,imx8qxp-dc-constframe
+
+  "^extdst@[0-9a-f]+$":
+    type: object
+    additionalProperties: true
+
+    properties:
+      compatible:
+        const: fsl,imx8qxp-dc-extdst
+
+  "^fetchdecode@[0-9a-f]+$":
+    type: object
+    additionalProperties: true
+
+    properties:
+      compatible:
+        const: fsl,imx8qxp-dc-fetchdecode
+
+  "^fetcheco@[0-9a-f]+$":
+    type: object
+    additionalProperties: true
+
+    properties:
+      compatible:
+        const: fsl,imx8qxp-dc-fetcheco
+
+  "^fetchlayer@[0-9a-f]+$":
+    type: object
+    additionalProperties: true
+
+    properties:
+      compatible:
+        const: fsl,imx8qxp-dc-fetchlayer
+
+  "^fetchwarp@[0-9a-f]+$":
+    type: object
+    additionalProperties: true
+
+    properties:
+      compatible:
+        const: fsl,imx8qxp-dc-fetchwarp
+
+  "^hscaler@[0-9a-f]+$":
+    type: object
+    additionalProperties: true
+
+    properties:
+      compatible:
+        const: fsl,imx8qxp-dc-hscaler
+
+  "^layerblend@[0-9a-f]+$":
+    type: object
+    additionalProperties: true
+
+    properties:
+      compatible:
+        const: fsl,imx8qxp-dc-layerblend
+
+  "^matrix@[0-9a-f]+$":
+    type: object
+    additionalProperties: true
+
+    properties:
+      compatible:
+        const: fsl,imx8qxp-dc-matrix
+
+  "^safety@[0-9a-f]+$":
+    type: object
+    additionalProperties: true
+
+    properties:
+      compatible:
+        const: fsl,imx8qxp-dc-safety
+
+  "^vscaler@[0-9a-f]+$":
+    type: object
+    additionalProperties: true
+
+    properties:
+      compatible:
+        const: fsl,imx8qxp-dc-vscaler
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - "#address-cells"
+  - "#size-cells"
+  - ranges
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/imx8-lpcg.h>
+
+    pixel-engine@56180800 {
+        compatible = "fsl,imx8qxp-dc-pixel-engine";
+        reg = <0x56180800 0xac00>;
+        clocks = <&dc0_lpcg IMX_LPCG_CLK_5>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ranges;
+
+        constframe@56180960 {
+            compatible = "fsl,imx8qxp-dc-constframe";
+            reg = <0x56180960 0x3>, <0x56184400 0x400>;
+            reg-names = "pec", "cfg";
+            fsl,dc-cf-id = <0>;
+        };
+
+        extdst@56180980 {
+            compatible = "fsl,imx8qxp-dc-extdst";
+            reg = <0x56180980 0x7>, <0x56184800 0x400>;
+            reg-names = "pec", "cfg";
+            interrupt-parent = <&dc0_intc>;
+            interrupts = <3>, <4>, <5>;
+            interrupt-names = "shdload", "framecomplete", "seqcomplete";
+            fsl,dc-ed-id = <0>;
+        };
+
+        constframe@561809a0 {
+            compatible = "fsl,imx8qxp-dc-constframe";
+            reg = <0x561809a0 0x3>, <0x56184c00 0x400>;
+            reg-names = "pec", "cfg";
+            fsl,dc-cf-id = <4>;
+        };
+
+        extdst@561809c0 {
+            compatible = "fsl,imx8qxp-dc-extdst";
+            reg = <0x561809c0 0x7>, <0x56185000 0x400>;
+            reg-names = "pec", "cfg";
+            interrupt-parent = <&dc0_intc>;
+            interrupts = <6>, <7>, <8>;
+            interrupt-names = "shdload", "framecomplete", "seqcomplete";
+            fsl,dc-ed-id = <4>;
+        };
+
+        constframe@561809e0 {
+            compatible = "fsl,imx8qxp-dc-constframe";
+            reg = <0x561809e0 0x3>, <0x56185400 0x400>;
+            reg-names = "pec", "cfg";
+            fsl,dc-cf-id = <1>;
+        };
+
+        extdst@56180a00 {
+            compatible = "fsl,imx8qxp-dc-extdst";
+            reg = <0x56180a00 0x7>, <0x56185800 0x400>;
+            reg-names = "pec", "cfg";
+            interrupt-parent = <&dc0_intc>;
+            interrupts = <9>, <10>, <11>;
+            interrupt-names = "shdload", "framecomplete", "seqcomplete";
+            fsl,dc-ed-id = <1>;
+        };
+
+        constframe@56180a20 {
+            compatible = "fsl,imx8qxp-dc-constframe";
+            reg = <0x56180a20 0x3>, <0x56185c00 0x400>;
+            reg-names = "pec", "cfg";
+            fsl,dc-cf-id = <5>;
+        };
+
+        extdst@56180a40 {
+            compatible = "fsl,imx8qxp-dc-extdst";
+            reg = <0x56180a40 0x7>, <0x56186000 0x400>;
+            reg-names = "pec", "cfg";
+            interrupt-parent = <&dc0_intc>;
+            interrupts = <12>, <13>, <14>;
+            interrupt-names = "shdload", "framecomplete", "seqcomplete";
+            fsl,dc-ed-id = <5>;
+        };
+
+        fetchwarp@56180a60 {
+            compatible = "fsl,imx8qxp-dc-fetchwarp";
+            reg = <0x56180a60 0x4>, <0x56186400 0x400>;
+            reg-names = "pec", "cfg";
+            fsl,dc-fw-id = <2>;
+        };
+
+        fetchlayer@56180ac0 {
+            compatible = "fsl,imx8qxp-dc-fetchlayer";
+            reg = <0x56180ac0 0x3>, <0x56188400 0x800>;
+            reg-names = "pec", "cfg";
+            fsl,dc-fl-id = <0>;
+        };
+
+        layerblend@56180ba0 {
+            compatible = "fsl,imx8qxp-dc-layerblend";
+            reg = <0x56180ba0 0x4>, <0x5618a400 0x400>;
+            reg-names = "pec", "cfg";
+            fsl,dc-lb-id = <0>;
+        };
+
+        layerblend@56180bc0 {
+            compatible = "fsl,imx8qxp-dc-layerblend";
+            reg = <0x56180bc0 0x4>, <0x5618a800 0x400>;
+            reg-names = "pec", "cfg";
+            fsl,dc-lb-id = <1>;
+        };
+
+        layerblend@56180be0 {
+            compatible = "fsl,imx8qxp-dc-layerblend";
+            reg = <0x56180be0 0x4>, <0x5618ac00 0x400>;
+            reg-names = "pec", "cfg";
+            fsl,dc-lb-id = <2>;
+        };
+
+        layerblend@56180c00 {
+            compatible = "fsl,imx8qxp-dc-layerblend";
+            reg = <0x56180c00 0x4>, <0x5618b000 0x400>;
+            reg-names = "pec", "cfg";
+            fsl,dc-lb-id = <3>;
+        };
+    };